Inventor
JAWARANI DHARMESH
US18 patents
⚠️ This page may combine multiple inventors who share the name “JAWARANI DHARMESH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
FREESCALE SEMICONDUCTOR INC
13 patentsUS8043888B2Oct 25, 2011
Phase change memory cell with heater and method therefor
FREESCALE SEMICONDUCTOR INC16 citations92
US7521314B2Apr 21, 2009
Method for selective removal of a layer
FREESCALE SEMICONDUCTOR INC29 citations92
US7544576B2Jun 9, 2009
Diffusion barrier for nickel silicides in a semiconductor fabrication process
FREESCALE SEMICONDUCTOR INC11 citations84
US7235473B2Jun 26, 2007
Dual silicide semiconductor fabrication process
FREESCALE SEMICONDUCTOR INC15 citations84
US7105429B2Sep 12, 2006
Method of inhibiting metal silicide encroachment in a transistor
FREESCALE SEMICONDUCTOR INC17 citations83
US7544575B2Jun 9, 2009
Dual metal silicide scheme using a dual spacer process
FREESCALE SEMICONDUCTOR INC12 citations81
US7262105B2Aug 28, 2007
Semiconductor device with silicided source/drains
FREESCALE SEMICONDUCTOR INC13 citations79
US7235471B2Jun 26, 2007
Method for forming a semiconductor device having a silicide layer
FREESCALE SEMICONDUCTOR INC8 citations73
US7622339B2Nov 24, 2009
EPI T-gate structure for CoSi2 extendibility
FREESCALE SEMICONDUCTOR INC2 citations63
US7510922B2Mar 31, 2009
Spacer T-gate structure for CoSi2 extendibility
FREESCALE SEMICONDUCTOR INC4 citations63
US7998822B2Aug 16, 2011
Semiconductor fabrication process including silicide stringer removal processing
FREESCALE SEMICONDUCTOR INC2 citations62
US7927934B2Apr 19, 2011
SOI semiconductor device with body contact and method thereof
FREESCALE SEMICONDUCTOR INC4 citations62
US7446006B2Nov 4, 2008
Semiconductor fabrication process including silicide stringer removal processing
FREESCALE SEMICONDUCTOR INC0 citations51