Inventor

BUYUKTOSUNOGLU ALPER

US191 patents

⚠️ This page may combine multiple inventors who share the name “BUYUKTOSUNOGLU ALPER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BUYUKTOSUNOGLU ALPER

IBM

Determining and storing bit error rate relationships in spin transfer torque magnetoresistive random-access memory (STT-MRAM)

Method and system for controlling power in a chip through a power-performance monitor and control unit

Cognitive computing for servers and mobile devices

Cognitive computing for servers and mobile devices

Determining and storing bit error rate relationships in spin transfer torque magnetoresistive random-access memory (STT-MRAM)

Dynamic temperature adjustments in spin transfer torque magnetoresistive random-access memory (STT-MRAM)

Hierarchical in-memory sort engine

Method and apparatus for conserving power by throttling instruction fetching when a processor encounters low confidence branches in an information handling system

Cost-conscious pre-emptive cache line displacement and relocation mechanisms

Method and structure for short range leakage control in pipelined circuits

Protecting against invalid memory references

On-chip supply noise voltage reduction or mitigation using local detection loops in a processor core

Generation and application of stressmarks in a computer system

Dynamic temperature adjustments in spin transfer torque magnetoresistive random-access memory (STT-MRAM)

Hierarchical in-memory sort engine

Dynamic detection of resource management anomalies in a processing system

Multi-threaded processor instruction balancing through instruction uncertainty

Method and system of multi-core microprocessor power management and control via per-chiplet, programmable power modes

Adaptive issue queue for reduced power at high performance

Methods for thermal management of three-dimensional integrated circuits

Systems and methods for mutually exclusive activation of microprocessor resources to control maximum power

Inducing heterogeneous microprocessor behavior using non-uniform cooling

Dynamic adjustments within memory systems

Proactive voltage droop reduction and/or mitigation in a processor core

Inducing heterogeneous microprocessor behavior using non-uniform cooling

Method and system of peak power enforcement via autonomous token-based control and management

Mitigating voltage droop

Determination and correction of physical circuit event related errors of a hardware design

Adaptive fetch gating in multithreaded processors, fetch control and method of controlling fetches

Adaptive multi-agent cooperative computation and inference

Hardware support for memory safety with an overflow table

Persistent power enabled on-chip data processor

Transparent interleaving of compressed cache lines

Clustering execution in a processing system to increase power savings

Space reduction in processor stressmark generation

Processor with memory-embedded pipeline for table-driven computation

Single thread cache miss rate estimation

Hierarchical in-memory sort engine

Power management for in-memory computer systems

Power management for multi-core processing systems

BOSE PRADIP

Systems and methods for thread assignment and core turn-off for integrated circuit energy efficiency and high-performance

Method and system for controlling power in a chip through a power-performance monitor and control unit

Method and system for controlling power in a chip through a power performance monitor and control unit

Managing instructions for more efficient load/store unit usage

Adaptive data prefetch

Adaptive workload based optimizations to mitigate current delivery limitations in integrated circuits

Guarded, multi-metric resource control for safe and efficient microprocessor management

Voltage regulator module with power gating and bypass

BASAK JAYANTA

Two-level guarded predictive power gating

Predictive power gating with optional guard mechanism