Inventor

VEMBU BALAJI

US297 patents

⚠️ This page may combine multiple inventors who share the name “VEMBU BALAJI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

VEMBU BALAJI

INTEL CORP

Instructions and logic to perform floating point and integer operations for machine learning

Instructions and logic to perform floating-point and integer operations for machine learning

Instructions and logic to perform floating point and integer operations for machine learning

Instructions and logic to perform floating-point and integer operations for machine learning

Instructions and logic to perform floating-point and integer operations for machine learning

Coordination and increased utilization of graphics processors during inference

Programmable coarse grained and sparse matrix compute hardware with advanced scheduling

Fault processing for direct memory access address translation

Caching support for direct memory access address translation

Apparatus and method for memory management in a graphics processing environment

Machine learning sparse computation mechanism

Apparatus and method for managing data bias in a graphics processing architecture

Compute cluster preemption within a general-purpose graphics processing unit

Machine learning sparse computation mechanism

Autonomous vehicle advanced sensing and response

Display engine surface blending and adaptive texel to pixel ratio sample rate system, apparatus and method

Programmable controller and command cache for graphics processors

Apparatus and method for memory address re-mapping of graphics data

Efficient thread group scheduling

Apparatus and method for managing data bias in a graphics processing architecture

Programmable coarse grained and sparse matrix compute hardware with advanced scheduling

Reduce power by frame skipping

Compute optimizations for neural networks using bipolar binary weight

Apparatus and method for efficient graphics virtualization

Specialized fixed function hardware for efficient convolution

Thread scheduling over compute blocks for power optimization

Graphics engine partitioning mechanism

Efficient multi-context thread distribution

Collaborative multi-user virtual reality

Compute optimization mechanism for deep neural networks

Compute optimizations for neural networks

Power management of memory chips based on working set size

Handling pipeline submissions across many compute units

Cloud based distributed single game calculation of shared computational work for multiple cloud gaming client devices

Extend GPU/CPU coherency to multi-GPU cores

Replacement policies for a hybrid hierarchical cache

Method and apparatus for authenticated, recoverable key distribution with no database secrets

Compute optimization mechanism for deep neural networks

Dynamic distributed training of machine learning models

Instructions and logic to perform floating point and integer operations for machine learning

Specialized fixed function hardware for efficient convolution

Thread scheduling over compute blocks for power optimization

VEMBU BALAJI

Memory address re-mapping of graphics data

Creating secure communication channels between processing elements

Method and apparatus for providing a secure display window inside the primary display

MCAFEE INC

Computing platform security methods and apparatus

Koston Joseph

Efficiently enqueuing workloads from user mode to hardware across privilege domains

KOKER ALTUG

Engine to enable high speed context switching via on-die storage

VEAL BRYAN E

Method and device to augment volatile memory in a graphics subsystem with non-volatile memory

COORAY NIRANJAN L

Apparatus and method for memory management in a graphics processing environment