Inventor
KAZDA MICHAEL
US5 patents
Patents
5 patentsUS11080456B2Aug 3, 2021
Automated design closure with abutted hierarchy
IBM4 citations66
US12585920B2Mar 24, 2026
Predicting optimal parameters for physical design synthesis
IBM0 citations48
US12282721B2Apr 22, 2025
Netlist design for post silicon local clock controller timing improvement
IBM0 citations47
US10831965B1Nov 10, 2020
Placement of vectorized latches in hierarchical integrated circuit development
IBM0 citations36
US10831967B1Nov 10, 2020
Local clock buffer controller placement and connectivity
IBM0 citations36