P

Inventor

SURTI PRASOONKUMAR

US367 patents
⚠️ This page may combine multiple inventors who share the name “SURTI PRASOONKUMAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

49 patents
US10304154B2May 28, 2019

Coordination and increased utilization of graphics processors during inference

INTEL CORP33 citations98
US11620256B2Apr 4, 2023

Systems and methods for improving cache efficiency and utilization

INTEL CORP36 citations97
US11113784B2Sep 7, 2021

Sparse optimizations for a matrix accelerator architecture

INTEL CORP46 citations97
US9912957B1Mar 6, 2018

Lossless compression for multisample render targets alongside fragment compression

INTEL CORP48 citations97
US11087522B1Aug 10, 2021

Apparatus and method for asynchronous ray tracing

INTEL CORP22 citations94
US10699465B1Jun 30, 2020

Cluster of scalar engines to accelerate intersection in leaf node

INTEL CORP21 citations94
US10893299B2Jan 12, 2021

Surface normal vector processing mechanism

INTEL CORP16 citations93
US10332320B2Jun 25, 2019

Autonomous vehicle advanced sensing and response

INTEL CORP26 citations93
US10109039B1Oct 23, 2018

Display engine surface blending and adaptive texel to pixel ratio sample rate system, apparatus and method

INTEL CORP13 citations93
US7719540B2May 18, 2010

Render-cache controller for multithreading, multi-core graphics processor

INTEL CORP35 citations93
US10546393B2Jan 28, 2020

Compression in machine learning and deep learning processing

INTEL CORP17 citations92
US10212443B2Feb 19, 2019

Lossless compression for multisample render targets alongside fragment compression

INTEL CORP12 citations92
US9754345B2Sep 5, 2017

Compression and decompression of graphics data using pixel region bit values

INTEL CORP17 citations92
US10817042B2Oct 27, 2020

Power savings for neural network architecture with zero activations during inference

INTEL CORP31 citations91
US12204487B2Jan 21, 2025

Graphics processor data access and sharing

INTEL CORP2 citations86
US11663746B2May 30, 2023

Systolic arithmetic on sparse data

INTEL CORP12 citations86
US10235735B2Mar 19, 2019

Graphics processor with tiled compute kernels

INTEL CORP15 citations86
US12210477B2Jan 28, 2025

Systems and methods for improving cache efficiency and utilization

INTEL CORP2 citations85
US12013808B2Jun 18, 2024

Multi-tile architecture for graphics operations

INTEL CORP3 citations85
US11954062B2Apr 9, 2024

Dynamic memory reconfiguration

INTEL CORP3 citations85
US11755501B2Sep 12, 2023

Efficient data sharing for graphics data processing operations

INTEL CORP9 citations85
US11676239B2Jun 13, 2023

Sparse optimizations for a matrix accelerator architecture

INTEL CORP10 citations85
US11178373B2Nov 16, 2021

Adaptive resolution of point cloud and viewpoint prediction for video streaming in computing environments

INTEL CORP9 citations85
US10911799B2Feb 2, 2021

Video refinement mechanism

INTEL CORP13 citations85
US10846814B2Nov 24, 2020

Patch processing mechanism

INTEL CORP18 citations85
US12182062B1Dec 31, 2024

Multi-tile memory management

INTEL CORP2 citations84
US12141094B2Nov 12, 2024

Systolic disaggregation within a matrix accelerator architecture

INTEL CORP2 citations84
US11995029B2May 28, 2024

Multi-tile memory management for detecting cross tile access providing multi-tile inference scaling and providing page migration

INTEL CORP2 citations84
US11399194B2Jul 26, 2022

Lossless compression for multisample render targets alongside fragment compression

INTEL CORP4 citations84
US11145105B2Oct 12, 2021

Multi-tile graphics processor rendering

INTEL CORP6 citations84
US11006138B2May 11, 2021

Lossless compression for multisample render targets alongside fragment compression

INTEL CORP6 citations84
US10929948B2Feb 23, 2021

Page cache system and method for multi-agent environments

INTEL CORP8 citations84
US10909039B2Feb 2, 2021

Data prefetching for graphics data processing

INTEL CORP5 citations84
US10880666B2Dec 29, 2020

Augmented reality virtual reality ray tracing sensory enhancement system, apparatus and method

INTEL CORP4 citations84
US10497084B2Dec 3, 2019

Efficient sharing and compression expansion of data across processing systems

INTEL CORP5 citations84
US10499073B2Dec 3, 2019

Lossless compression for multisample render targets alongside fragment compression

INTEL CORP7 citations84
US10452397B2Oct 22, 2019

Efficient multi-context thread distribution

INTEL CORP7 citations84
US10430147B2Oct 1, 2019

Collaborative multi-user virtual reality

INTEL CORP9 citations84
US10423415B2Sep 24, 2019

Hierarchical general register file (GRF) for execution block

INTEL CORP9 citations84
US10417731B2Sep 17, 2019

Compute optimization mechanism for deep neural networks

INTEL CORP8 citations84
US10410115B2Sep 10, 2019

Autonomous machines through cloud, error corrections, and predictions

INTEL CORP10 citations84
US10387160B2Aug 20, 2019

Shared local memory tiling mechanism

INTEL CORP7 citations84
US10365843B2Jul 30, 2019

Power management of memory chips based on working set size

INTEL CORP8 citations84
US10282808B2May 7, 2019

Hierarchical lossless compression and null data support

INTEL CORP9 citations84
US10261903B2Apr 16, 2019

Extend GPU/CPU coherency to multi-GPU cores

INTEL CORP8 citations84
US10251011B2Apr 2, 2019

Augmented reality virtual reality ray tracing sensory enhancement system, apparatus and method

INTEL CORP7 citations84
US10157493B2Dec 18, 2018

Adaptive multisampling based on vertex attributes

INTEL CORP5 citations84
US10109078B1Oct 23, 2018

Controlling coarse pixel size from a stencil buffer

INTEL CORP5 citations84
US9984430B2May 29, 2018

Ordering threads as groups in a multi-threaded, multi-core graphics compute system

INTEL CORP9 citations84

SURTI PRASOONKUMAR

1 patent

Showing the top 50 of 367 patents by PatentIndex Score.