Inventor

EITAN AMRAM

US19 patents

⚠️ This page may combine multiple inventors who share the name “EITAN AMRAM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

EITAN AMRAM

INTEL CORP

Microelectronic package interconnect and method of fabrication thereof

Microelectronic structures having multiple microelectronic devices connected with a microelectronic bridge embedded in a microelectronic substrate

Thermal compression bonding process cooling manifold

Electronic package that includes fine powder coating

Microelectronic package interconnect and method of fabrication thereof

Electronic assembly that includes a bridge

Microelectronic structures having multiple microelectronic devices connected with a microelectronic bridge embedded in a microelectronic substrate

Thermal compression bonding process cooling manifold

Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates

Microelectronics package comprising a package-on-package (PoP) architecture with inkjet barrier material for controlling bondline thickness and PoP adhesive keep out zone

Microelectronics package comprising a package-on-package (PoP) architecture with inkjet barrier material for controlling bondline thickness and pop adhesive keep out zone

Microelectronics package comprising a package-on-package (POP) architecture with inkjet barrier material for controlling bondline thickness and POP adhesive keep out zone

Microelectronic structures having multiple microelectronic devices connected with a microelectronic bridge embedded in a microelectronic substrate

Method, system, and apparatus for filling vias

In-situ formation of conductive filling material in through-silicon via

Two material high K thermal encapsulant system

TAIWAN SEMICONDUCTOR MFG CO LTD

Die bonding tool with tiltable bond head for improved bonding and methods for performing the same

Bonding structures for semiconductor devices and methods of forming the same

DIAS RAJENDRA C

Ablation method and recipe for wafer level underfill material patterning and removal