Inventor

AGARWAL RAJAT

IN84 patents

⚠️ This page may combine multiple inventors who share the name “AGARWAL RAJAT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

AGARWAL RAJAT

INTEL CORP

Error detection and correction apparatus and method

Silent data corruption mitigation using error correction code with embedded signaling fault detection

Internal error checking and correction (ECC) with extra system bits

Dynamic application of error correction code (ECC) based on error type

Mitigating silent data corruption in a buffered memory module architecture

Memory replay mechanism

Low overhead integrity protection with high availability for trust domains

Read retry to selectively disable on-die ECC

Interconnect architecture with silicon interposer and EMIB

Memory with reduced exposure to manufacturing related data corruption errors

Integrated heat spreader that maximizes heat transfer from a multi-chip package

Thermal throttling of electronic devices

Method, system and apparatus for reducing memory traffic in a distributed memory system

Mechanism to generate logically dedicated read and write channels in a memory controller

Adaptive error correction to improve system memory reliability, availability, and serviceability (RAS)

Read retry to selectively disable on-die ECC

DIMM for a high bandwidth memory channel

Apparatus and method for implementing a multi-level memory hierarchy

Cryptographic system memory management

Method and apparatus for partial cache line sparing

System, apparatus and method for overriding of non-locality-based instruction handling

Apparatus and method for implementing a multi-level memory hierarchy

Apparatus and method for implementing a multi-level memory hierarchy having different operating modes

Method and apparatus for partial cache line sparing

Error correction code memory security

Apparatus, system, and method to flush modified data from a volatile memory to a persistent second memory

Method and apparatus for reverse memory sparing

Cryptographic system memory management

Technologies for fast booting with error-correcting code memory

Cryptographic system memory management

Apparatus and method for implementing a multi-level memory hierarchy having different operating modes

Key rotating trees with split counters for efficient hardware replay protection

High bandwidth DIMM

Synchronized memory channels with unidirectional links

Distribution of error checking and correction (ECC) bits to allocate ECC bits for metadata

Interconnect architecture with silicon interposer and EMIB

Apparatus and method to reduce bandwidth and latency overheads of probabilistic caches

Efficient security metadata encoding in error correcting code (ECC) memory without dedicated ECC bits

RAMANUJAN RAJ K

Apparatus and method for implementing a multi-level memory hierarchy having different operating modes

Apparatus and method for implementing a multi-level memory hierarchy

AHUJA SANDEEP

Integrated heat spreader that maximizes heat transfer from a multi-chip package

HENKEL AG & CO KGAA

Epoxy compositions having improved impact resistance

RADHAKRISHNAN SIVAKUMAR

Power management using adaptive thermal throttling

ALEXANDER JAMES W

Fully buffered DIMM read data substitution for write acknowledgement

SAMSUNG ELECTRONICS CO LTD

Method and apparatus for storing, processing and reconstructing full resolution image out of sub band encoded images

DAS DEBALEENA

Enhanced storage of metadata utilizing improved error detection and correction in computer memory

AGARWAL RAJAT

Poison bit error checking code scheme

CHRISTENSON BRUCE A

Memory controller using time-staggered lockstep sub-channels with buffered memory

HOLLMAN FAMILY ADVISORS LLC

Secure work pod

UNIV CONNECTICUT

Method for coating metals by dip autopolymerization