Inventor

MUENCH ROBERT

DE35 patents

⚠️ This page may combine multiple inventors who share the name “MUENCH ROBERT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MUENCH ROBERT

PACT XPP TECHNOLOGIES AG

Runtime configurable arithmetic and logic cell

Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity

Runtime configurable arithmetic and logic cell

Method of repairing integrated circuits

Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs , etc.)

Method for deadlock-free configuration of dataflow processors and modules with a two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)

I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures

Reconfigurable multidimensional array processor allowing runtime reconfiguration of selected individual array cells

Process for automatic dynamic reloading of data flow processors (DFPS) and units with two- or three- dimensional programmable cell architectures (FPGAS, DPGAS, and the like)

I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures

Method of self-synchronization of configurable elements of a programmable module

Method of hierarchical caching of configuration data having dataflow processors and modules having two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)

Method and system for alternating between programs for execution by cells of an integrated circuit

I/O and memory bus system for DFPs and units with two-or multi-dimensional programmable cell architectures

Run-time reconfiguration method for programmable units

I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures

Method of self-synchronization of configurable elements of a programmable unit

PACT GMBH

Method of self-synchronization of configurable elements of a programmable module

Method of self-synchronization of configurable elements of a programmable unit

I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures

Process for automatic dynamic reloading of data flow processors (dfps) and units with two-or-three-dimensional programmable cell architectures (fpgas, dpgas, and the like)

Unit for processing numeric and logic operations for use in central processing units (cpus), multiprocessor systems, data-flow processors (dsps), systolic processors and field programmable gate arrays (epgas)

I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures

I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures

Process for automatic dynamic reloading of data flow processors (DFPs) and units with two or three-dimensional programmable cell architectures (FPGAs, DPGAs and the like)

Method of the self-synchronization of configurable elements of a programmable unit

Run-time reconfiguration method for programmable units

Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity

VORBACH MARTIN

Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like)

Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs

I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures

Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units

I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures

PACT INF TECH GMBH

Method for hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)--

Method for the automatic address generation of modules within clusters comprised of a plurality of these modules