Inventor

RAKSHIT TITASH

US84 patents

⚠️ This page may combine multiple inventors who share the name “RAKSHIT TITASH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RAKSHIT TITASH

SAMSUNG ELECTRONICS CO LTD

Multi-VT gate stack for III-V nanosheet devices with reduced parasitic capacitance

Method and system for performing analog complex vector-matrix multiplication

Multi-bit, SoC-compatible neuromorphic weight cell using ferroelectric FETs

Giant spin hall-based compact neuromorphic cell optimized for differential read inference

Horizontal nanosheet FETs and methods of manufacturing the same

Gate-all-around field effect transistors with horizontal nanosheet conductive channel structures for MOL/inter-channel spacing and related cell architectures

High-density neuromorphic computing element

Monolithic multi-bit weight cell for neuromorphic computing

Integrated circuit including field effect transistors having a contact on active gate compatible with a small cell area having a small contacted poly pitch

Ferroelectric-based memory cell usable in on-logic chip memory

Selectorless 3D stackable memory

Semiconductor device including a repeater/buffer at higher metal routing layers and methods of manufacturing the same

Zero leakage, high noise margin coupled giant spin hall based retention latch

0T bi-directional memory cell

High-density neuromorphic computing element

High-density neuromorphic computing element

Monolithic multi-bit weight cell for neuromorphic computing

Method of enabling sparse neural networks on memresistive accelerators

Giant spin hall-based compact neuromorphic cell optimized for differential read inference

Multi-bit, SoC-compatible neuromorphic weight cell using ferroelectric FETs

Method and system for training of neural networks using continuously differentiable models

Semiconductor device including a repeater/buffer at upper metal routing layers and methods of manufacturing the same

Giant spin hall-based compact neuromorphic cell optimized for differential read inference

4T4R ternary weight cell with high on/off ratio background

Vertical optical via and method of fabrication

INTEL CORP

Stacked multi-gate transistor design and method of fabrication

Quantum well MOSFET channels having uni-axial strain caused by metal source/drains, and conformal regrowth source/drains

Replacement spacers for MOSFET fringe capacitance reduction and processes of making same

Quantum well MOSFET channels having uni-axial strain caused by metal source/drains, and conformal regrowth source/drains

Schottky barrier metal-germanium contact in metal-germanium-metal photodetectors

Quantum well MOSFET channels having lattice mismatch with metal source/drains, and conformal regrowth source/drains

Silicon and silicon germanium nanowire structures

Increasing body dopant uniformity in multi-gate transistor devices

Apparatus and methods for improving multi-gate device performance

Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin

Stress in trigate devices using complimentary gate fill materials

Multi-gate III-V quantum well structures

Compositionally-graded quantum-well channels for semiconductor devices

Semiconductor device with reduced fringe capacitance

KUHN KELIN J

Silicon and silicon germanium nanowire structures

Silicon and silicon germanium nanowire structures

MAJHI PRASHANT

Quantum well MOSFET channels having uni-axial strain caused by metal source/drains, and conformal regrowth source/drains

Method of forming quantum well mosfet channels having uni-axial strains caused by metal source/drains

PILLARISETTY RAVI

Modulation-doped halo in quantum well field-effect transistors, apparatus made therewith, and methods of using same

Double quantum well structures for transistors

RAKSHIT TITASH

Trigate transistor having extended metal gate electrode

OBRADOVIC BORNA J

Multi-layer fin field effect transistor devices and methods of forming the same

SYNC COMPUTING CORP

Real time scheduling using expected application resource usage

SONY GROUP CORP

Silicon and silicon germanium nanowire structures

SONY CORP

Silicon and silicon germanium nanowire structures