Inventor
CHEN JAU-WEN
US13 patents
⚠️ This page may combine multiple inventors who share the name “CHEN JAU-WEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
LSI CORP
6 patentsUS7582938B2Sep 1, 2009
I/O and power ESD protection circuits by enhancing substrate-bias in deep-submicron CMOS process
LSI CORP28 citations91
US7375543B2May 20, 2008
Electrostatic discharge testing
LSI CORP6 citations62
US7948036B2May 24, 2011
I/O and power ESD protection circuits by enhancing substrate-bias in deep-submicron CMOS process
LSI CORP2 citations61
US7763908B2Jul 27, 2010
Design of silicon-controlled rectifier by considering electrostatic discharge robustness in human-body model and charged-device model devices
LSI CORP4 citations61
US7551414B2Jun 23, 2009
Electrostatic discharge series protection
LSI CORP1 citations51
US7777996B2Aug 17, 2010
Circuit protection system
LSI CORP1 citations48
LSI LOGIC CORP
5 patentsUS6347026B1Feb 12, 2002
Input and power protection circuit implemented in a complementary metal oxide semiconductor process using salicides
LSI LOGIC CORP37 citations88
US6979869B2Dec 27, 2005
Substrate-biased I/O and power ESD protection circuits in deep-submicron twin-well process
LSI LOGIC CORP43 citations86
US7119405B2Oct 10, 2006
Implantation method to improve ESD robustness of thick gate-oxide grounded-gate NMOSFET's in deep-submicron CMOS technologies
LSI LOGIC CORP14 citations78
US7317228B2Jan 8, 2008
Optimization of NMOS drivers using self-ballasting ESD protection technique in fully silicided CMOS process
LSI LOGIC CORP4 citations61
US7379281B2May 27, 2008
Bias for electrostatic discharge protection
LSI LOGIC CORP1 citations46