Inventor

ADUSUMILLI SIVA P

US110 patents

⚠️ This page may combine multiple inventors who share the name “ADUSUMILLI SIVA P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ADUSUMILLI SIVA P

GLOBALFOUNDRIES US INC

Structure including resistor network for back biasing FET stack

Unlanded thermal dissipation pillar adjacent active contact

Photodetector array with diffraction gratings having different pitches

Device integration schemes leveraging a bulk semiconductor substrate having a &lt;111 &gt; crystal orientation

Waveguide with attenuator

Grating couplers integrated with one or more airgaps

Multi-depth regions of high resistivity in a semiconductor substrate

Photodetector with reflector with air gap adjacent photodetecting region

Heterojunction bipolar transistors with one or more sealed airgap

Field-effect transistors with vertically-serpentine gates

Silicon photonic components fabricated using a bulk substrate

Transistor with embedded isolation layer in bulk substrate

Photodiode and/or PIN diode structures

Active attack prevention for secure integrated circuits using latchup sensitive diode circuit

Active x-ray attack prevention device

Sealed cavity structures with a planar surface

High electron mobility transistor devices having a silicided polysilicon layer

Photodetector with buried airgap reflectors

Vertically stacked field effect transistors

III-V compound semiconductor layer stacks with electrical isolation provided by a trap-rich layer

Photodetector with buried airgap reflectors

Vertically stacked field effect transistors

Cavity formation within and under semiconductor devices

Structure providing poly-resistor under shallow trench isolation and above high resistivity polysilicon layer

Microfluidic channels in a substrate with a surface covered by a layer stack

Photodetector structure with air gap and related methods

Device integration schemes leveraging a bulk semiconductor substrate having a &lt;111&gt; crystal orientation

Switches in bulk substrate

Field effect transistor with shallow trench isolation features within source/drain regions

Photodiodes

Device integration schemes leveraging a bulk semiconductor substrate having a &lt;111&gt; crystal orientation

Airgap structures in auto-doped region under one or more transistors

GLOBALFOUNDRIES INC

Bulk substrates with a self-aligned buried polycrystalline layer

Methods of forming an isolated nano-sheet transistor device and the resulting device

Radio frequency switches with air gap structures

Vertical field effect transistor formation with critical dimension control

Sealed cavity structures with a planar surface

Waveguides with multiple airgaps arranged in and over a silicon-on-insulator substrate

Sealed cavity structures with non-planar surface features to induce stress

Waveguides with multiple-level airgaps

Radio frequency switches with air gap structures

Bulk substrates with a self-aligned buried polycrystalline layer

Heterojunction bipolar transistors having bases with different elevations

Through-silicon vias for heterogeneous integration of semiconductor device structures

Electro-optic modulator with vertically-arranged optical paths

Substrates with self-aligned buried dielectric and polycrystalline layers

Semiconductor device with airgap spacer for transistor and related method

Neuromorphic circuit structure and method to form same

Method of forming an integrated circuit (IC) with shallow trench isolation (STI) regions and the resulting IC structure

Field-effect transistors with laterally-serpentine gates

Device integration schemes leveraging a bulk semiconductor substrate having a <111 > crystal orientation

Device integration schemes leveraging a bulk semiconductor substrate having a <111> crystal orientation

Device integration schemes leveraging a bulk semiconductor substrate having a <111> crystal orientation