Inventor

HARTSTEIN ALLAN M

US28 patents

⚠️ This page may combine multiple inventors who share the name “HARTSTEIN ALLAN M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HARTSTEIN ALLAN M

IBM

Micromechanical display logic and array

Branch history guided instruction/data prefetching

Low voltage memory

Prefetching using future branch path information derived from branch prediction

Method and apparatus for prefetching branch history information

Artificial ionic synapse

Neural network having an associative memory that learns by example

Photon assisted tunneling testing of passivated integrated circuits

Solid state battery

Photon assisted tunneling testing of passivated integrated circuits

Method of making short channel IGFET

Three-dimensional processing system having independent calibration and statistical collection layer

Three-dimensional processing system having at least one layer with circuitry dedicated to scan testing and system state checkpointing of other system layers

Voltage controlled resonant transmission semiconductor device

Three-dimensional processing system having at least one layer with circuitry dedicated to scan testing and system state checkpointing of other system layers

Three-dimensional computer processor systems having multiple local power and cooling layers and a global interconnection structure

Memory architectures having wiring structures that enable different access patterns in multiple dimensions

BUYUKTOSUNOGLU ALPER

3-D stacked multiprocessor structures and methods to enable reliable operation of processors at speeds above specified limits

3-D stacked multiprocessor structure with vertically aligned identical layout operating processors in independent mode or in sharing mode running faster components

3-D stacked multiprocessor structures and methods for multimodal operation of same

3-D stacked multiprocessor structures and methods for multimodal operation of same

3-D stacked multiprocessor structure with vertically aligned identical layout operating processors in independent mode or in sharing mode running faster components

3-D stacked multiprocessor structures and methods to enable reliable operation of processors at speeds above specified limits

EMMA PHILIP G

Branch prediction instructions having mask values involving unloading and loading branch history data

Executing touchBHT instruction to pre-fetch information to prediction mechanism for branch with taken history

Branch prediction path wrong guess instruction

GLOBALFOUNDRIES INC

Three-dimensional processing system having multiple caches that can be partitioned, conjoined, and managed according to more than one set of rules and/or configurations

Memory architectures having wiring structures that enable different access patterns in multiple dimensions