Inventor

HEALY MICHAEL B

US36 patents

⚠️ This page may combine multiple inventors who share the name “HEALY MICHAEL B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HEALY MICHAEL B

IBM

Selective memory error reporting

Error monitoring of a memory device containing embedded error correction

Thermal-aware memory

Error monitoring of a memory device containing embedded error correction

Thermal-aware memory

Detecting a cryogenic attack on a memory device with embedded error correction

Memory system with switchable operating bands

Memory device error history bit

Selective memory error reporting

Memory device error history bit

Error monitoring of a memory device containing embedded error correction

Latency-agnostic memory controller

Three-dimensional processing system having independent calibration and statistical collection layer

Three-dimensional processing system having at least one layer with circuitry dedicated to scan testing and system state checkpointing of other system layers

Built-in self-test for embedded spin-transfer torque magnetic random access memory

Memory system with switchable operating bands

Extended error correction coding data storage

Extended error correction coding data storage

Error vector readout from a memory device

Error vector readout from a memory device

Three-dimensional processing system having at least one layer with circuitry dedicated to scan testing and system state checkpointing of other system layers

Three-dimensional computer processor systems having multiple local power and cooling layers and a global interconnection structure

Memory architectures having wiring structures that enable different access patterns in multiple dimensions

Servicing indirect data storage requests with multiple memory controllers

Partitioned memory with locally aggregated copy pools

Partitioned memory with locally aggregated copy pools

Systems, methods and computer program products using multi-tag storage for efficient data compression in caches

Aggregating, disaggregating and converting electronic transaction request messages

BUYUKTOSUNOGLU ALPER

3-D stacked multiprocessor structures and methods to enable reliable operation of processors at speeds above specified limits

3-D stacked multiprocessor structure with vertically aligned identical layout operating processors in independent mode or in sharing mode running faster components

3-D stacked multiprocessor structures and methods for multimodal operation of same

3-D stacked multiprocessor structures and methods for multimodal operation of same

3-D stacked multiprocessor structure with vertically aligned identical layout operating processors in independent mode or in sharing mode running faster components

3-D stacked multiprocessor structures and methods to enable reliable operation of processors at speeds above specified limits

GLOBALFOUNDRIES INC

Three-dimensional processing system having multiple caches that can be partitioned, conjoined, and managed according to more than one set of rules and/or configurations

Memory architectures having wiring structures that enable different access patterns in multiple dimensions