Inventor

PANDITA BUPESH

US20 patents

⚠️ This page may combine multiple inventors who share the name “PANDITA BUPESH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PANDITA BUPESH

QUALCOMM INC

Gate boosted low drop regulator

Hybrid phase-locked loop

Pulse to digital converter

Apparatus and method for combining currents from passive equalizer in sense amplifier

Fractional phase locked loop (PLL) architecture

Quadrature clock generation with injection locking

Apparatus and method for frequency calibration of voltage controlled oscillator (VCO) including determining VCO frequency range

Delay locked loop (DLL) employing pulse to digital converter (PDC) for calibration

Apparatus and method for in situ analog signal diagnostic and debugging with calibrated analog-to-digital converter

Linear equalizer with variable gain

Phase locked loop (PLL) architecture

Serializer-deserializer with frequency doubler

SerDes with adaptive clock data recovery

Low-power, low-latency time-to-digital-converter-based serial link

MICROSOFT TECHNOLOGY LICENSING LLC

Network transceiver with VGA channel specific equalization

Phase-locked-loop circuit employing a hybrid loop filter with sample and hold capacitors for reduced signal jitter, and related methods

Phase-locked loops (PLL), including time-to-digital converter (TDC) gain calibration circuits and related methods

Network transceiver with VGA channel specific equalization

Adaptive channel equalization for a duo-binary transceiver

Programmable analog calibration circuit supporting iterative measurement of an input signal from a measured circuit, such as for calibration, and related methods