Inventor
DENEROFF MARTIN M
US29 patents
⚠️ This page may combine multiple inventors who share the name “DENEROFF MARTIN M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
SILICON GRAPHICS INC
18 patentsUS5504874AApr 2, 1996
System and method of implementing read resources to maintain cache coherency in a multiprocessor environment permitting split transactions
SILICON GRAPHICS INC131 citations99
US6751698B1Jun 15, 2004
Multiprocessor node controller circuit and method
SILICON GRAPHICS INC210 citations98
US5272664ADec 21, 1993
High memory capacity DRAM SIMM
SILICON GRAPHICS INC177 citations97
US6215686B1Apr 10, 2001
Memory system with switching for data isolation
SILICON GRAPHICS INC122 citations96
US7406086B2Jul 29, 2008
Multiprocessor node controller circuit and method
SILICON GRAPHICS INC65 citations95
US7197589B1Mar 27, 2007
System and method for providing access to a bus
SILICON GRAPHICS INC22 citations93
US6115278ASep 5, 2000
Memory system with switching for data isolation
SILICON GRAPHICS INC86 citations93
US6973559B1Dec 6, 2005
Scalable hypercube multiprocessor network for massive parallel processing
SILICON GRAPHICS INC19 citations92
US6877030B2Apr 5, 2005
Method and system for cache coherence in DSM multiprocessor system without growth of the sharing vector
SILICON GRAPHICS INC28 citations92
US5664151ASep 2, 1997
System and method of implementing read resources to maintain cache coherency in a multiprocessor environment permitting split transactions
SILICON GRAPHICS INC24 citations92
US5509125AApr 16, 1996
System and method for fair arbitration on a multi-domain multiprocessor bus
SILICON GRAPHICS INC30 citations92
US6829666B1Dec 7, 2004
Modular computing architecture having common communication interface
SILICON GRAPHICS INC30 citations89
US6516372B1Feb 4, 2003
Partitioning a distributed shared memory multiprocessor computer to facilitate selective hardware maintenance
SILICON GRAPHICS INC44 citations89
US6845410B1Jan 18, 2005
System and method for a hierarchical system management architecture of a highly scalable computing system
SILICON GRAPHICS INC29 citations88
US6339812B1Jan 15, 2002
Method and apparatus for handling invalidation requests to processors not present in a computer system
SILICON GRAPHICS INC7 citations72
US7181589B2Feb 20, 2007
System and method for performing address translation in a computer system
SILICON GRAPHICS INC5 citations63
US7398359B1Jul 8, 2008
System and method for performing memory operations in a computing system
SILICON GRAPHICS INC1 citations61
US6578115B2Jun 10, 2003
Method and apparatus for handling invalidation requests to processors not present in a computer system
SILICON GRAPHICS INC4 citations61
SILICON GRAPHICS INTERNAT
3 patentsUS7802058B1Sep 21, 2010
Method for performing cache coherency in a computer system
SILICON GRAPHICS INTERNAT26 citations92
US7881321B2Feb 1, 2011
Multiprocessor node controller circuit and method
SILICON GRAPHICS INTERNAT14 citations89
US7925839B1Apr 12, 2011
System and method for performing memory operations in a computing system
SILICON GRAPHICS INTERNAT2 citations61