Inventor
COE DWIFUZI
US4 patents
⚠️ This page may combine multiple inventors who share the name “COE DWIFUZI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
3 patentsUS10572387B2Feb 25, 2020
Hardware control of CPU hold of a cache line in private cache where cache invalidate bit is reset upon expiration of timer
IBM1 citations59
US10691604B2Jun 23, 2020
Minimizing cache latencies using set predictors
IBM0 citations50
US10684951B2Jun 16, 2020
Minimizing cache latencies using set predictors
IBM0 citations50