Inventor

HAMPEL CRAIG E

US253 patents

⚠️ This page may combine multiple inventors who share the name “HAMPEL CRAIG E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HAMPEL CRAIG E

RAMBUS INC

Method and apparatus for signaling between devices of a memory system

Low power memory device

System for a memory device having a power down mode and method

Method and apparatus for signaling between devices of a memory system

Method and apparatus for configuring access times of memory devices

Multiple channel modules and bus systems using same

System with phase jumping locked loop circuit

Power control system for synchronous memory device

Apparatus and method for topography dependent signaling

Method and apparatus for coordinating memory operations among diversely-located memory components

Apparatus and method for topography dependent signaling

High performance cost optimized memory

Methods and systems for reducing heat flux in memory systems

Method and apparatus for two step memory write operations

DRAM core refresh with reduced spike current

Apparatus and method for topography dependent signaling

Rambus DRAM (RDRAM) apparatus and method for performing refresh operations

Power control system for synchronous memory device

Method and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domain

High performance cost optimized memory with delayed memory writes

Dram core refresh with reduced spike current

Memory error detection

Memory error detection

Memory module with reduced access granularity

Memory device with mode-selectable prefetch and clock-to-core timing

Timing calibration apparatus and method for a memory device signaling system

Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules

Apparatus and method for thermal regulation in memory subsystems

Apparatus and method for thermal regulation in memory subsystems

Method and apparatus for coordinating memory operations among diversely-located memory components

Memory device with clock multiplier circuit

Method, system and memory controller utilizing adjustable write data delay settings

Method, system and memory controller utilizing adjustable read data delay settings

Apparatus and method for topography dependent signaling

High performance cost optimized memory

Memory module with offset data lines and bit line swizzle configuration

Memory system with channel multiplexing of multiple memory devices

DRAM core refresh with reduced spike current

DRAM core refresh with reduced spike current

Memory module

Memory component with terminated and unterminated signaling inputs

Upgradable memory system with reconfigurable interconnect

Integrated circuit device and signaling method with topographic dependent equalization coefficient

Periodic calibration for communication channels by drift tracking

WARE FREDERICK A

Communication channel calibration for drift conditions

Memory controller with selective data transmission delay

Memory module with termination component

Memory controller device having timing offset capability

INTEL CORP

Memory device and system including a low power interface

STOTT BRET G

Signaling system with adaptive timing calibration