Inventor
GEMELLI RICCARDO
IT18 patents
⚠️ This page may combine multiple inventors who share the name “GEMELLI RICCARDO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ITALTEL SPA
7 patentsUS6970966B2Nov 29, 2005
System of distributed microprocessor interfaces toward macro-cell based designs implemented as ASIC or FPGA bread boarding and relative common bus protocol
ITALTEL SPA65 citations94
US7130942B2Oct 31, 2006
Interface bus protocol for managing transactions in a system of distributed microprocessor interfaces toward marco-cell based designs implemented as ASIC or FPGA bread boarding
ITALTEL SPA36 citations90
US7082563B2Jul 25, 2006
Automated method for generating the cyclic redundancy check for transmission of multi-protocol packets
ITALTEL SPA34 citations84
US7289502B1Oct 30, 2007
Method and device for routing or compressing packets destination address containing classless address
ITALTEL SPA17 citations80
US6549536B1Apr 15, 2003
Method of address compression for cell-based and packet-based protocols and hardware implementations thereof
ITALTEL SPA8 citations72
US6964574B2Nov 15, 2005
Daughter board for a prototyping system
ITALTEL SPA8 citations66
US7036095B2Apr 25, 2006
Clock generation system for a prototyping apparatus
ITALTEL SPA5 citations57
ST MICROELECTRONICS INT NV
3 patentsUS10860415B2Dec 8, 2020
Memory architecture including response manager for error correction circuit
ST MICROELECTRONICS INT NV0 citations50
US10379937B2Aug 13, 2019
Memory architecture including response manager for error correction circuit
ST MICROELECTRONICS INT NV0 citations50
US10528422B2Jan 7, 2020
Redundant storage of error correction code (ECC) checkbits for validating proper operation of a static random access memory (SRAM)
ST MICROELECTRONICS INT NV0 citations49
CUCCHI SILVIO
2 patentsST MICROELECTRONICS GRENOBLE 2
2 patentsUS11055173B2Jul 6, 2021
Redundant storage of error correction code (ECC) checkbits for validating proper operation of a static random access memory (SRAM)
ST MICROELECTRONICS GRENOBLE 22 citations70
US11436162B2Sep 6, 2022
Functional safety method, corresponding system-on-chip, device and vehicle
ST MICROELECTRONICS GRENOBLE 20 citations49