Inventor

LLOYD BRYAN

US48 patents

⚠️ This page may combine multiple inventors who share the name “LLOYD BRYAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LLOYD BRYAN

IBM

Virtual cache tag renaming for synonym handling

Address translation for sending real address to memory subsystem in effective address based load-store unit

Hazard detection of out-of-order execution of load and store instructions in processors without using real addresses

Address translation for sending real address to memory subsystem in effective address based load-store unit

Load-hit-load detection in an out-of-order processor

Executing load-store operations without address translation hardware per load-store unit port

Handling and fusing load instructions in a processor

Virtual cache synonym detection using alias tags

Virtual cache mechanism for program break point register exception handling

Hazard detection of out-of-order execution of load and store instructions in processors without using real addresses

Handling effective address synonyms in a load-store unit that operates without address translation

Handling effective address synonyms in a load-store unit that operates without address translation

Handling effective address synonyms in a load-store unit that operates without address translation

Handling effective address synonyms in a load-store unit that operates without address translation

Gather buffer management for unaligned and gather load operations

Prefetch store preallocation in an effective address-based cache directory

Executing load-store operations without address translation hardware per load-store unit port

Efficient store-forwarding with partitioned FIFO store-reorder queue in out-of-order processor

Speculative finish of instruction execution in a processor core

Speculative finish of instruction execution in a processor core

Context tracking for multiple virtualization layers in a virtually tagged cache

Detection of conflicts between transactions and page shootdowns

Gather buffer management for unaligned and gather load operations

Microprocessor that fuses load and compare instructions

Processor overriding of a false load-hit-store detection

Translation bandwidth optimized prefetching strategy through multiple translation lookaside buffers

Virtual cache tag renaming for synonym handling

Area and power efficient mechanism to wakeup store-dependent loads according to store drain merges

Load-store unit with partitioned reorder queues with single cam port

Load-store unit with partitioned reorder queues with single cam port

Virtual cache synonym detection using alias tags

Speculatively releasing store data before store instruction completion in a processor

Execution elision of intermediate instruction by processor

Dynamic translation lookaside buffer (TLB) invalidation using virtually tagged cache for load/store operations

Tracking load and store instructions and addresses in an out-of-order processor

Tracking load and store instructions and addresses in an out-of-order processor

Dispatching, allocating, and deallocating instructions with real/virtual and region tags in a queue in a processor

Effective address based load store unit in out of order processors

Effective address based load store unit in out of order processors

Handling effective address synonyms in a load-store unit that operates without address translation

Prioritization of threads in a simultaneous multithreading processor core

Marking in-flight requests affected by translation entry invalidation in a data processing system

Writing store data of multiple store operations into a cache line in a single cycle

Handling oversize store to load forwarding in a processor

Executing load-store operations without address translation hardware per load-store unit port

Allocating and deallocating reorder queue entries for an out-of-order processor

CAIN III HAROLD W

Detection of conflicts between transactions and page shootdowns

BUSABA FADI YUSUF

Systems and methods for implementing logic in a processor