P

Inventor

TAO ZHENG

BE23 patents
⚠️ This page may combine multiple inventors who share the name “TAO ZHENG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IMEC VZW

19 patents
US11107812B2Aug 31, 2021

Method of fabricating stacked semiconductor device

IMEC VZW2 citations71
US9899220B2Feb 20, 2018

Method for patterning a substrate involving directed self-assembly

IMEC VZW2 citations71
US10090393B2Oct 2, 2018

Method for forming a field effect transistor device having an electrical contact

IMEC VZW2 citations70
US11776841B2Oct 3, 2023

Buried power rail contact formation

IMEC VZW0 citations61
US12512417B2Dec 30, 2025

Method and structure for determining an overlay error

IMEC VZW0 citations60
US11862452B2Jan 2, 2024

Contact isolation in semiconductor devices

IMEC VZW0 citations60
US11824122B2Nov 21, 2023

Method for filling a space in a semiconductor

IMEC VZW0 citations60
US12451429B2Oct 21, 2025

Interconnection structure for a semiconductor device

IMEC VZW0 citations55
US12237207B2Feb 25, 2025

Method for forming a buried metal line in a semiconductor substrate

IMEC VZW0 citations50
US11430697B2Aug 30, 2022

Method of forming a mask layer

IMEC VZW0 citations50
US10153341B2Dec 11, 2018

Method of forming internal spacer for nanowires

IMEC VZW1 citations50
US12538779B2Jan 27, 2026

Method for producing a buried interconnect rail of an integrated circuit chip

IMEC VZW0 citations49
US10493378B2Dec 3, 2019

Method of forming micro-pipes on a substrate and a structure formed thereof

IMEC VZW0 citations47
US12381116B2Aug 5, 2025

Method of manufacturing an interconnection structure for a semiconductor device having a spacer separating first and second conductive lines

IMEC VZW0 citations44
US10128371B2Nov 13, 2018

Self-aligned nanostructures for semiconductor devices

IMEC VZW0 citations41
US10825682B2Nov 3, 2020

Method for producing a pillar structure in a semiconductor layer

IMEC VZW0 citations40
US9520291B2Dec 13, 2016

Method of providing an implanted region in a semiconductor structure

IMEC VZW0 citations40
US10790382B2Sep 29, 2020

Method for forming horizontal nanowires and devices manufactured thereof

IMEC VZW0 citations36
US9548208B2Jan 17, 2017

Method for patterning an underlying layer

IMEC VZW0 citations34

BYD CO LTD

2 patents

UNISANTIS ELECT SINGAPORE PTE

1 patent

STARSE ENERGY AND TECH GROUP CO LTD

1 patent