Inventor

YEH JENG-YA D

US21 patents

⚠️ This page may combine multiple inventors who share the name “YEH JENG-YA D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YEH JENG-YA D

INTEL CORP

High voltage three-dimensional devices having dielectric liners

Transistor architecture having extended recessed spacer and source/drain regions and method of making same

CMOS-compatible polycide fuse structure and method of fabricating same

Non-planar semiconductor device having self-aligned fin with top blocking layer

Antifuse element utilizing non-planar topology

Vertical non-planar semiconductor device for system-on-chip (SoC) applications

High voltage three-dimensional devices having dielectric liners

High voltage three-dimensional devices having dielectric liners

High voltage three-dimensional devices having dielectric liners

High voltage three-dimensional devices having dielectric liners

High voltage three-dimensional devices having dielectric liners

High voltage three-dimensional devices having dielectric liners

Vertical non-planar semiconductor device for system-on-chip (SoC) applications

High voltage three-dimensional devices having dielectric liners

Low leakage non-planar access transistor for embedded dynamic random access memory (eDRAM)

HAFEZ WALID M

Antifuse element utilizing non-planar topology

High voltage three-dimensional devices having dielectric liners

High voltage three-dimensional devices having dielectric liners

YEH JENG-YA D

Precision resistor for non-planar semiconductor device architecture

Precision resistor for non-planar semiconductor device architecture

JAN CHIA-HONG

Multi-gate transistors