Inventor

MORRIS BRIAN S

US31 patents

⚠️ This page may combine multiple inventors who share the name “MORRIS BRIAN S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MORRIS BRIAN S

INTEL CORP

Mapping a physical address differently to different memory devices in a group

Techniques for probabilistic dynamic random access memory row repair

Protect non-memory encryption engine (non-mee) metadata in trusted execution environment

Shared buffered memory routing

Speculative reads in buffered memory

Error handling in transactional buffered memory

Techniques for determining victim row addresses in a volatile memory

Supporting configurable security levels for memory address ranges

Method and apparatus for partial cache line sparing

Techniques for probabilistic dynamic random access memory row repair

Supporting configurable security levels for memory address ranges

Method and apparatus for partial cache line sparing

Early identification in transactional buffered memory

Apparatuses and methods to accelerate matrix multiplication

Sharing memory and I/O services between nodes

Supporting multiple memory types in a memory slot

Packed write completions

Method and apparatus for reverse memory sparing

Techniques for determining victim row addresses in a volatile memory

Sharing memory and I/O services between nodes

Sharing memory and I/O services between nodes

Shared buffered memory routing

Shared buffered memory routing

Shared buffered memory routing

Early identification in transactional buffered memory

Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device

Implementation of reserved cache slots in computing system having inclusive/non inclusive tracking and two level system memory

Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device

Error handling in transactional buffered memory

MORRIS BRIAN S

Virtual device sparing

HONEYWELL INT INC

Electrical connector backshell assemblies