Inventor

IACULO MASSIMO

IT48 patents

⚠️ This page may combine multiple inventors who share the name “IACULO MASSIMO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IACULO MASSIMO

MICRON TECHNOLOGY INC

NAND data placement schema

Controller to manage NAND memories

Reading sequential data from memory using a pivot table

Clustered parity for NAND data placement schema

NAND data placement schema

Scheme to improve efficiency of device garbage collection in memory devices

Scheme to improve efficiency of garbage collection in cached flash translation layer

NAND logical-to-physical table region tracking

Hybrid logical to physical caching scheme

Controlling NAND operation latency

Controlling NAND operation latency

Controlling NAND operation latency

Log data storage for flash memory

Virtual partition management in a memory device

Real-time trigger to dump an error log

Clustered parity for NAND data placement schema

NAND data placement schema

Controller to manage NAND memories

Controller to manage NAND memories

Allocation schema for a scalable memory area

Data defragmentation for a system boot procedure having random indexes indicating a relationship between sequential logical addresses and random logical addresses

Hybrid logical to physical caching scheme of L2P cache and L2P changelog

Allocation schema for a scalable memory area

Wear leveling for erasable memories

Idle mode temperature control for memory systems

Data relocation operation techniques

Idle mode temperature control for memory systems

Data relocation operation techniques

Virtual partition management

Virtual partition management in a memory device

Log data storage for flash memory

Fatal error logging in a memory device

Fatal error logging in a memory device

Real-time trigger to dump an error log

Corrupted storage portion recovery in a memory device

Adaptive data relocation for improved data management for memory

Read disturb management for memory

Data caching for fast system boot-up

Device fault condition reporting

Instruction caching scheme for memory devices

Memory buffer having accessible information after a program-fail

IACULO MASSIMO

Method for managing bad memory blocks in a nonvolatile-memory device, and nonvolatile-memory device implementing the management method

Wear leveling for erasable memories

Preparation of memory device for access using memory access type indicator signal

TIZIANI FEDERICO

Controller to execute error correcting code algorithms and manage NAND memories

ZANARDI STEFANO

Secure memory device erase

LODESTAR LICENSING GROUP LLC

NAND logical-to-physical table region tracking

PASQUALE CIMMINO

Memory buffer having accessible information after a program-fail