Inventor
LE JIAYONG
US13 patents
⚠️ This page may combine multiple inventors who share the name “LE JIAYONG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
SYNOPSYS INC
8 patentsUS8843864B2Sep 23, 2014
Statistical corner evaluation for complex on-chip variation model
SYNOPSYS INC18 citations90
US8713501B1Apr 29, 2014
Dual-box location aware and dual-bitmap voltage domain aware on-chip variation techniques
SYNOPSYS INC14 citations82
US11288426B2Mar 29, 2022
Analyzing delay variations and transition time variations for electronic circuits
SYNOPSYS INC0 citations61
US10783301B2Sep 22, 2020
Analyzing delay variations and transition time variations for electronic circuits
SYNOPSYS INC0 citations50
US10255395B2Apr 9, 2019
Analyzing delay variations and transition time variations for electronic circuits
SYNOPSYS INC0 citations50
US12112108B2Oct 8, 2024
Method to compute timing yield and yield bottleneck using correlated sample generation and efficient statistical simulation
SYNOPSYS INC0 citations49
US10755023B1Aug 25, 2020
Circuit timing analysis
SYNOPSYS INC0 citations47
US9424380B2Aug 23, 2016
Augmented simulation method for waveform propagation in delay calculation
SYNOPSYS INC0 citations36
CELIK MUSTAFA
3 patentsUS7890915B2Feb 15, 2011
Statistical delay and noise calculation considering cell and interconnect variations
CELIK MUSTAFA190 citations96
US7487486B2Feb 3, 2009
Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations
CELIK MUSTAFA18 citations91
US8495544B2Jul 23, 2013
Statistical delay and noise calculation considering cell and interconnect variations
CELIK MUSTAFA5 citations71