Inventor

ADAR ETAI

IL20 patents

⚠️ This page may combine multiple inventors who share the name “ADAR ETAI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ADAR ETAI

IBM

PCI-to-PCI bridges with a timer register for storing a delayed transaction latency

Direct memory access between an accelerator and a processor using a coherency adapter

Method of optimizing buffer usage of virtual channels of a physical communication link and apparatuses for performing the same

Managing lowest point of coherency (LPC) memory using a service layer adapter

Direct memory access between an accelerator and a processor using a coherency adapter

Device, system, and method of speculative packet transmission

Direct memory access between an accelerator and a processor using a coherency adapter

Device, system, and method of handling transactions

Coordination of spare lane usage between link partners

Data mask coding

Coordination of spare lane usage between link partners

Signal phase verification for systems incorporating two synchronous clock domains

Device, system, and method of handling delayed transactions

ADAR ETAI

PCI express error handling and recovery action controls

Performance monitor design for counting events generated by thread groups

Sharing sampled instruction address registers for efficient instruction sampling in massively multithreaded processors

Performance monitor design for instruction profiling using shared counters

Detection of frame marker quality

Polling of a target register within a peripheral device

GRANOVSKY ILYA

Decode data for fast PCI express multi-function device address decode