Inventor

ZAGORIANAKOS STEVEN W

US23 patents

⚠️ This page may combine multiple inventors who share the name “ZAGORIANAKOS STEVEN W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ZAGORIANAKOS STEVEN W

NETRONOME SYSTEMS INC

Configuration mesh data bus and transactional memories in a multi-processor integrated circuit

Configuration mesh data bus and transactional memories in a multi-processor integrated circuit

Chained-instruction dispatcher

Flow control using a local event ring in an island-based network flow processor

Command-driven NFA hardware engine that encodes multiple automatons

Automaton hardware engine employing memory-efficient transition table indexing

Distributed credit FIFO link of a configurable mesh data bus

In-flight packet processing

Return available PPI credits command

Using a credits available value in determining whether to issue a PPI allocation request to a packet engine

Guaranteed in-order packet delivery

CPP bus transaction value having a PAM/LAM selection code field

NFA completion notification

Transactional memory having local CAM and NFA resources

NFA byte detector

Registered FIFO

STARK GAVIN J

Commonality of memory island interface and structure

Island-based network flow processor integrated circuit

Flow control using a local event ring in an island-based network flow processor

Distributed credit FIFO link of a configurable mesh data bus

Processing resource management in an island-based network flow processor

INTEL CORP

Configuring queues based on a given parameter

Dual bus memory controller