Inventor

LIN YI-HSIUNG

TW63 patents

⚠️ This page may combine multiple inventors who share the name “LIN YI-HSIUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIN YI-HSIUNG

TAIWAN SEMICONDUCTOR MFG CO LTD

Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure

Transistors with varying width nanosheet

Buried metal track and methods forming same

Metal rail conductors for non-planar semiconductor devices

Integrated circuit and method of manufacturing same

Fin field effect transistor device structure and method for forming the same

Buried metal track and methods forming same

Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure

Method of forming butted contact

Methods of forming contact features in field-effect transistors

Metal rail conductors for non-planar semiconductor devices

Fin field effect transistor device structure

Semiconductor device with contact structures

Methods of forming contact features in field-effect transistors

Integrated circuit device including a power supply line and method of forming the same

Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure

Vertical semiconductor device structure and method of forming

Method of forming masks

Methods of forming metal layer structures in semiconductor devices

Methods of forming metal layer structures in semiconductor devices

Implanter calibration

Implanter calibration

Transistors with varying width nanosheet

Interconnect structure and methods thereof

FinFET SRAM cells with reduced fin pitch

Semiconductor device with contact structures

Methods of forming contact features in field-effect transistors

Metal rail conductors for non-planar semiconductor devices

Integrated circuit device including a power supply line and method of forming the same

Method for forming fin field effect transistor device structure

Integrated circuit device including a power supply line and method of forming the same

Fin field effect transistor device structure

Formation method of semiconductor device with contact structures

Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure

FinFET SRAM cells with reduced fin pitch

Interconnect structure and methods thereof

Capacitance reduction by metal cut design

Integrated circuit structure

Buried metal track and methods forming same

Integrated circuit and method of manufacturing same

Methods and structures of novel contact feature

IBM

Dual damascene structure and method

Method of patterning damascene structure in integrated circuit design

Multiple layer resist scheme implementing etch recipe particular to each layer

SAMSUNG ELECTRONICS CO LTD

Methods of forming electrical interconnect structures using polymer residues to increase etching selectivity through dielectric layers

Method of fabricating interconnections of microelectronic device using dual damascene process

INFINEON TECHNOLOGIES AG

Process for forming fusible links

UNITED MICROELECTRONICS CORP

Method of forming embedded capacitor structure applied to logic integrated circuit

YUAN YIN MACHINERY IND CO LTD

Hat ironing machine

LIN YI-HSIUNG

Cooler