Inventor

FROUGIER JULIEN

US247 patents

⚠️ This page may combine multiple inventors who share the name “FROUGIER JULIEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FROUGIER JULIEN

GLOBALFOUNDRIES INC

Methods of forming nanosheet transistor with dielectric isolation of source-drain regions and related structure

Structures and SRAM bit cells with a buried cross-couple interconnect

Work function metal patterning for N-P space between active nanostructures

Nanosheet field-effect transistors including a two-dimensional semiconducting material

Hybrid gate-all-around (GAA) field effect transistor (FET) structure and method of forming

Complementary FETs with wrap around contacts and method of forming same

Inner spacer formation for nanosheet field-effect transistors with tall suspensions

Methods of forming a nano-sheet transistor device with a thicker gate stack and the resulting device

Vertically stacked complementary-FET device with independent gate control

Insulated epitaxial structures in nanosheet complementary field effect transistors

Insulative structure with diffusion break integral with isolation layer and methods to form same

Inner spacer formation in a nanosheet field-effect transistor

Forming self-aligned gate and source/drain contacts using sacrificial gate cap spacer and resulting devices

Wrap-around contacts formed with multiple silicide layers

Stacked nanosheet field-effect transistor with air gap spacers

Complementary FETs with wrap around contacts and methods of forming same

Structures and SRAM bit cells integrating complementary field-effect transistors

Fin-type field-effect transistors including a two-dimensional material

Method, apparatus, and system for fin-over-nanosheet complementary field-effect-transistor

Method of forming air-gap spacers and gate contact over active region and the resulting device

Nanosheet field-effect transistors formed with sacrificial spacers

Vertically stacked complementary-FET device with independent gate control

Gate-all-around field effect transistors with air-gap inner spacers and methods

Vertical field effect transistors incorporating U-shaped semiconductor bodies and methods

Vertical FET with self-aligned source/drain regions and gate length based on channel epitaxial growth process

Method of forming gate-all-around (GAA) FinFET and GAA FinFET formed thereby

Methods, apparatus and system for forming wrap-around contact with dual silicide

Wrap-all-around contact for nanosheet-FET and method of forming same

IBM

Integration of air spacer with self-aligned contact in transistor

Nanosheet FET with box isolation on substrate

Forming nanosheet transistor using sacrificial spacer and inner spacers

Stacked spin-orbit-torque magnetoresistive random-access memory

Formation of dielectric layer as etch-stop for source and drain epitaxy disconnection

Negative-capacitance steep-switch field effect transistor with integrated bi-stable resistive system

Non-self aligned gate contacts formed over the active region of a transistor

Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism

Steep-switch field effect transistor with integrated bi-stable resistive system

Stacked FET SRAM

Semiconductor device having a backside power rail

Gate-all-around monolithic stacked field effect transistors having multiple threshold voltages

Moon-shaped bottom spacer for vertical transport field effect transistor (VTFET) devices

Moon-shaped bottom spacer for vertical transport field effect transistor (VTFET) devices

Semiconductor structures with power rail disposed under active gate

Nanosheet-based semiconductor structure with dielectric pillar

Dual dielectric pillar fork sheet device

Airgap gate spacer

Semiconductor device with airgap spacer formation from backside of wafer

GLOBALFOUNDRIES US INC

Gate-all-around field effect transistors with robust inner spacers and methods

Field-effect transistors with channel regions that include a two-dimensional material on a mandrel

ADEIA SEMICONDUCTOR SOLUTIONS LLC

Forming nanosheet transistor using sacrificial spacer and inner spacers