Inventor

CASSETTI DAVID K

US12 patents

⚠️ This page may combine multiple inventors who share the name “CASSETTI DAVID K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

VLSI TECHNOLOGY INC

5 patents

US5781802AJul 14, 1998

First-in-first-out (FIFO) controller for buffering data between systems which are asynchronous and free of false flags and internal metastability

VLSI TECHNOLOGY INC24 citations91

US5794072AAug 11, 1998

Timing method and apparatus for interleaving PIO and DMA data transfers

VLSI TECHNOLOGY INC54 citations90

US5842012ANov 24, 1998

Efficient soft reset in a personal computer

VLSI TECHNOLOGY INC16 citations73

US5696938ADec 9, 1997

Computer system permitting mulitple write buffer read-arounds and method therefor

VLSI TECHNOLOGY INC11 citations73

US5535360AJul 9, 1996

Digital computer system having an improved direct-mapped cache controller (with flag modification) for a CPU with address pipelining and method therefor

VLSI TECHNOLOGY INC16 citations72

INTEL CORP

5 patents

US8370274B2Feb 5, 2013

VLSI TECHNOLOGY

1 patent

US5752262AMay 12, 1998

System and method for enabling and disabling writeback cache

VLSI TECHNOLOGY14 citations72

CASSETTI DAVID K

1 patent

US9223618B2Dec 29, 2015

Multi-threaded queuing system for pattern matching

CASSETTI DAVID K0 citations40

CASSETTI DAVID K

VLSI TECHNOLOGY INC

First-in-first-out (FIFO) controller for buffering data between systems which are asynchronous and free of false flags and internal metastability

Timing method and apparatus for interleaving PIO and DMA data transfers

Efficient soft reset in a personal computer

Computer system permitting mulitple write buffer read-arounds and method therefor

Digital computer system having an improved direct-mapped cache controller (with flag modification) for a CPU with address pipelining and method therefor

INTEL CORP

Apparatuses and methods for deterministic pattern matching

Compression engine with configurable search depths and window sizes

Selection of data compression technique based on input characteristics

Compression scheme with control of search agent activity

Multi-threaded queuing system for pattern matching

VLSI TECHNOLOGY

System and method for enabling and disabling writeback cache

CASSETTI DAVID K

Multi-threaded queuing system for pattern matching