Inventor
DONG ZHONG
US22 patents
⚠️ This page may combine multiple inventors who share the name “DONG ZHONG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
PROMOS TECHNOLOGIES INC
10 patentsUS7122415B2Oct 17, 2006
Atomic layer deposition of interpoly oxides in a non-volatile memory device
PROMOS TECHNOLOGIES INC67 citations97
US7001810B2Feb 21, 2006
Floating gate nitridation
PROMOS TECHNOLOGIES INC22 citations92
US7910429B2Mar 22, 2011
Method of forming ONO-type sidewall with reduced bird's beak
PROMOS TECHNOLOGIES INC28 citations91
US7323729B2Jan 29, 2008
Methods for improving quality of high temperature oxide (HTO) formed from halogen-containing precursor and products thereof and apparatus therefor
PROMOS TECHNOLOGIES INC7 citations73
US7071127B2Jul 4, 2006
Methods for improving quality of semiconductor oxide composition formed from halogen-containing precursor
PROMOS TECHNOLOGIES INC8 citations73
US6849897B2Feb 1, 2005
Transistor including SiON buffer layer
PROMOS TECHNOLOGIES INC8 citations73
US7297597B2Nov 20, 2007
Method for simultaneously fabricating ONO-type memory cell, and gate dielectrics for associated high voltage write transistors and gate dielectrics for low voltage logic transistors by using ISSG
PROMOS TECHNOLOGIES INC6 citations62
US7229880B2Jun 12, 2007
Precision creation of inter-gates insulator
PROMOS TECHNOLOGIES INC6 citations62
US6893920B2May 17, 2005
Method for forming a protective buffer layer for high temperature oxide processing
PROMOS TECHNOLOGIES INC2 citations62
US7265015B2Sep 4, 2007
Use of chlorine to fabricate trench dielectric in integrated circuits
PROMOS TECHNOLOGIES INC3 citations61
CHARTERED SEMICONDUCTOR MFG
4 patentsUS6534388B1Mar 18, 2003
Method to reduce variation in LDD series resistance
CHARTERED SEMICONDUCTOR MFG37 citations92
US6187633B1Feb 13, 2001
Method of manufacturing a gate structure for a semiconductor memory device with improved breakdown voltage and leakage rate
CHARTERED SEMICONDUCTOR MFG29 citations87
US6524910B1Feb 25, 2003
Method of forming dual thickness gate dielectric structures via use of silicon nitride layers
CHARTERED SEMICONDUCTOR MFG13 citations84
US6261976B1Jul 17, 2001
Method of forming low pressure silicon oxynitride dielectrics having high reliability
CHARTERED SEMICONDUCTOR MFG18 citations84
PROMOS TECHNOLOGIES PTE LTD
4 patentsUS7851339B2Dec 14, 2010
Method of repairing deep subsurface defects in a silicon substrate that includes diffusing negatively charged ions into the substrate from a sacrificial oxide layer
PROMOS TECHNOLOGIES PTE LTD2 citations62
US7387972B2Jun 17, 2008
Reducing nitrogen concentration with in-situ steam generation
PROMOS TECHNOLOGIES PTE LTD4 citations60
US7807577B2Oct 5, 2010
Fabrication of integrated circuits with isolation trenches
PROMOS TECHNOLOGIES PTE LTD1 citations52
US7737487B2Jun 15, 2010
Nonvolatile memories with tunnel dielectric with chlorine
PROMOS TECHNOLOGIES PTE LTD0 citations51