Inventor

DRAPALA GARRETT MICHAEL

US6 patents

⚠️ This page may combine multiple inventors who share the name “DRAPALA GARRETT MICHAEL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

QUALCOMM INC

3 patents

US11550723B2Jan 10, 2023

Method, apparatus, and system for memory bandwidth aware data prefetching

QUALCOMM INC2 citations70

US11226910B2Jan 18, 2022

Ticket based request flow control

QUALCOMM INC0 citations60

US11016899B2May 25, 2021

Selectively honoring speculative memory prefetch requests based on bandwidth state of a memory access path component(s) in a processor-based system

QUALCOMM INC0 citations48

IBM

2 patents

US9892043B2Feb 13, 2018

Nested cache coherency protocol in a tiered multi-node computer system

IBM5 citations83

US9720833B2Aug 1, 2017

Nested cache coherency protocol in a tiered multi-node computer system

IBM8 citations83

DRAPALA GARRETT MICHAEL

1 patent

US9727464B2Aug 8, 2017

Nested cache coherency protocol in a tiered multi-node computer system

DRAPALA GARRETT MICHAEL1 citations45