Inventor
JAMES FELICIA
US14 patents
Patents
14 patentsUS9875325B2Jan 23, 2018
Computer implemented system and method of identification of useful untested states of an electronic design
ZIPALOG INC8 citations82
US10963608B2Mar 30, 2021
System and method for passive verification
ZIPALOG INC1 citations71
US10262093B2Apr 16, 2019
Computer implemented system and method of identification of useful untested states of an electronic design
ZIPALOG INC1 citations71
US10402505B2Sep 3, 2019
Computer implemented system and method of translation of verification commands of an electronic design
ZIPALOG INC3 citations69
US11657201B2May 23, 2023
Computer implemented system and method of identification of useful untested states of an electronic design
ZIPALOG INC0 citations61
US11003824B2May 11, 2021
Computer implemented system and method of identification of useful untested states of an electronic design
ZIPALOG INC0 citations61
US11704448B2Jul 18, 2023
Computer implemented system and method of translation of verification commands of an electronic design
ZIPALOG INC0 citations59
US11074373B2Jul 27, 2021
Computer implemented system and method of translation of verification commands of an electronic design
ZIPALOG INC0 citations59
US10691857B2Jun 23, 2020
Computer implemented system and method of identification of useful untested states of an electronic design
ZIPALOG INC0 citations50
US10599793B2Mar 24, 2020
System and method for passive verification
ZIPALOG INC0 citations50
US10339237B2Jul 2, 2019
System and method for passive verification
ZIPALOG INC0 citations50
US9886536B2Feb 6, 2018
System and method for passive verification
ZIPALOG INC0 citations50
US10621290B2Apr 14, 2020
Computer implemented system and method of translation of verification commands of an electronic design
ZIPALOG INC0 citations48
US9715566B2Jul 25, 2017
Computer implemented system and method of translation of verification commands of an electronic design
ZIPALOG INC0 citations48