Inventor

SCHMISSEUR MARK A

US77 patents

⚠️ This page may combine multiple inventors who share the name “SCHMISSEUR MARK A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SCHMISSEUR MARK A

INTEL CORP

Memory sharing for physical accelerator resources in a data center

Technologies for dynamic allocation of tiers of disaggregated memory resources

Disaggregated physical memory resources in a data center

Method, system, and program for handling input/output commands

Method, system, and program for configuring components on a bus for input/output operations

Apparatus and method for a base address register on a computer peripheral device supporting configuration and testing of address space size

Method and system for syndrome generation and data recovery

Allocating cache lines

Technolgies for millimeter wave rack interconnects

Method and apparatus for dynamically allocating storage resources to compute nodes

Techniques to configure a solid state drive to operate in a storage mode or a memory mode

Virtual serial presence detect for pooled memory

Providing data integrity for data streams

Application aware memory patrol scrubbing techniques

Method, system, and program for managing data transfer and construction

Method, system, and program for generating parity data

Method, system, and program for returning data to read requests received over a bus

Scalable edge computing

Method and apparatus for dynamically allocating storage resources to compute nodes

Scalable edge computing

Multi-tenant edge cloud system power management

Adaptive data migration across disaggregated memory resources

Arbitration across shared memory pools of disaggregated memory devices

Method and apparatus for dynamically allocating storage resources to compute nodes

Techniques to configure a solid state drive to operate in a storage mode or a memory mode

Method, system, and program for handling Input/Output commands

Techniques to control quality of service for end-to-end paths in a compute environment

Shared memory for intelligent network interface cards

Tenant based allocation for pooled memory

Techniques to control quality of service for end-to-end paths in a compute environment

Shared memory for intelligent network interface cards

Method and apparatus to manage flush of an atomic group of writes to persistent memory in response to an unexpected power loss

Efficient and scalable cyclic redundancy check circuit using Galois-field arithmetic

Persistent memory write semantics on PCIe with existing TLP definition

Memory schemes for infrastructure processing unit architectures

Platform data aging for adaptive memory scaling

Scalable edge computing

Memory controller to manage quality of service enforcement and migration between local and pooled memory

Technologies for providing a split memory pool for full rack connectivity

Filtering training data for models in a data center

Techniques for dynamic multi-storage format database access

Storing and retrieving training data for models in a data center

Inbound and outbound message passing between a host processor and I/O processor local memory

Techniques to control quality of service for end-to-end paths in a compute environment

System decoder for training accelerators

Shared memory for intelligent network interface cards

System decoder for training accelerators

Ballooning for multi-tiered pooled memory

RADHAKRISHNAN SIVAKUMAR

Efficient and scalable cyclic redundancy check circuit using Galois-field arithmetic

RAMANUJAN RAJ K

Apparatus and method for phase change memory drift management