Inventor

RAMANUJAN RAJ K

US70 patents

⚠️ This page may combine multiple inventors who share the name “RAMANUJAN RAJ K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RAMANUJAN RAJ K

INTEL CORP

Memory channel that supports near memory and far memory access

Memory channel that supports near memory and far memory access

Memory channel that supports near memory and far memory access

Two-level system main memory

High performance interconnect

Techniques for probabilistic dynamic random access memory row repair

Two-level system main memory

Memory channel that supports near memory and far memory access

High performance interconnect

Method and apparatus for dynamically allocating storage resources to compute nodes

Apparatus and method for managing subscription requests for a network interface component

High performance interconnect

High performance interconnect

Technologies for quality of service based throttling in fabric architectures

Method and apparatus for cache line write back operation

Dynamic partial power down of memory-side cache in a 2-level memory hierarchy

Method and apparatus for dynamically allocating storage resources to compute nodes

Apparatus and method for implementing a multi-level memory hierarchy

Memory channel that supports near memory and far memory access

Two-level system main memory

Apparatus and method for implementing a multi-level memory hierarchy

Apparatus and method for implementing a multi-level memory hierarchy having different operating modes

Techniques for probabilistic dynamic random access memory row repair

Accelerating boot time zeroing of memory based on non-volatile memory (NVM) technology

Method and apparatus for store durability and ordering in a persistent memory architecture

Refresh of data stored in a cross-point non-volatile memory

Hybrid memory device

High performance interconnect

High performance interconnect

Non-uniform memory access latency adaptations to achieve bandwidth quality of service

Reliable replication mechanisms based on active-passive HFI protocols built on top of non-reliable multicast fabric implementations

Non-uniform memory access latency adaptations to achieve bandwidth quality of service

Memory card with volatile and non volatile memory space having multiple usage model configurations

Clearing poison status on read accesses to volatile memory regions allocated in non-volatile memory

Persistent memory write semantics on PCIe with existing TLP definition

RAMANUJAN RAJ K

Apparatus and method for implementing a multi-level memory hierarchy over common memory channels

Apparatus and method for implementing a multi-level memory hierarchy having different operating modes

Apparatus and method for implementing a multi-level memory hierarchy

Statistical wear leveling for non-volatile system memory

Bad block management mechanism

Dynamic partial power down of memory-side cache in a 2-level memory hierarchy

Apparatus and method for phase change memory drift management

DIGITAL EQUIPMENT CORP

Cache memory system

Method and apparatus for high speed data transmission between two systems operating under the same clock with unknown and non constant skew in the clock between the two systems

System for flushing instruction-cache only when instruction-cache address and data-cache address are matched and the execution of a return-from-exception-or-interrupt command

Cache with at least two fill rates

Lockout registers

NALE BILL

Memory channel that supports near memory and far memory access

KHAN JAWAD B

Method and system for data de-duplication

DAHLEN ERIC J

Two-level system main memory