Inventor

RAPPOPORT LIHU

IL45 patents

⚠️ This page may combine multiple inventors who share the name “RAPPOPORT LIHU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RAPPOPORT LIHU

INTEL CORP

Instruction segment recording scheme

Correlated address prediction

Method and system for branch target prediction using path information

Cache structure for storing variable length data

Cache structure for storing variable length data

Controlling population size of confidence assignments

Cache memory bank access prediction

Defragmented and efficient micro-operation cache

Apparatuses and methods for speculative execution side channel mitigation

Apparatuses and methods for a processor architecture

Technology for dynamically tuning processor features

Apparatuses and methods for speculative execution side channel mitigation

Automatic predication of hard-to-predict convergent branches

Apparatus and method for efficient memory renaming prediction using virtual registers

Apparatuses and methods for a processor architecture

Technology for dynamically tuning processor features

Detecting a dynamic control flow re-convergence point for conditional branches in hardware

Technology for dynamically tuning processor features

Accelerating memory fault resolution by performing fast re-fetching

Accelerating memory fault resolution by performing fast re-fetching

Memory cache bank prediction

Criticality based port scheduling

Trace indexing via trace end addresses

System, apparatus and method for context-based override of history-based branch predictions

Code prefetch instruction

De-prioritizing speculative code lines in on-chip caches

Method and apparatus for predicting values in a processor having a plurality of prediction modes

Multicore system for fusing instructions queued during a dynamically adjustable time window

Optimizing performance of instructions based on sequence detection or information associated with the instructions

Memory cache bank prediction

Region aware delta prefetcher

Device, method, and system to facilitate improved bandwidth of a branch prediction unit

Hybrid threading

Thread pause processors, methods, systems, and instructions

Instruction and logic for register based hardware memory renaming

Instruction length decoder system and method

RAPPOPORT LIHU

Efficient method and apparatus for employing a micro-op cache in a processor

Method and apparatus for inclusion of TLB entries in a micro-op cache of a processor

Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor

Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor

YIGZAW THEODROS

Apparatus and method for implement a multi-level memory hierarchy

OUZIEL IDO

System and method for fusing instructions queued during a time window defined by a delay counter

FALIK OHAD

Optimizing performance of instructions based on sequence detection or information associated with the instructions

KIM ILHYUN

Multi-level tracking of in-use state of cache lines

RAIKIN SHLOMO

Protecting the integrity of binary translated code