Inventor

STRAIT GARY E

US23 patents

⚠️ This page may combine multiple inventors who share the name “STRAIT GARY E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

STRAIT GARY E

IBM

Error correcting scheme

Memory management for a symmetric multiprocessor computer system

Bad wordline/array detection in memory

Distributed shared resource management

Increased bandwidth of ordered stores in a non-uniform memory subsystem

Increased bandwidth of ordered stores in a non-uniform memory subsystem

Maintaining order with parallel access data streams

Directly initiating by external adapters the setting of interruption initiatives

Method, system, and computer program product for merging data

Matrix and compression-based error detection

Matrix and compression-based error detection

Method, system and computer program product for enhanced shared store buffer management scheme for differing buffer sizes with limited resources for optimized performance

Dual/multi-mode processor pipelines sampling

Dual/multi-mode processor pipeline sampling

Queue management for multiway queues

Peer to peer job monitoring and control in grid computing systems

Deadlock avoidance in a multi-processor computer system with extended cache line locking

STRAIT GARY E

Method, system and computer program product for enhanced shared store buffer management scheme with limited resources for optimized performance

Method, system and computer program product for data buffers partitioned from a cache array

CHECK MARK A

Memory error isolation and recovery in a multiprocessor computer system

MEANEY PATRICK J

Bad wordline/array detection in memory

HAGSPIEL NORBERT

Memory ordered store system in a multiprocessor computer system

DUNN DEANNA POSTLES

Merging data in an L2 cache memory