Inventor
SREENIVAS ADITYA
US38 patents
Patents
38 patentsUS6885374B2Apr 26, 2005
Apparatus, method and system with a graphics-rendering engine having a time allocator
INTEL CORP68 citations98
US7103730B2Sep 5, 2006
Method, system, and apparatus for reducing power consumption of a memory
INTEL CORP107 citations97
US6628294B1Sep 30, 2003
Prefetching of virtual-to-physical address translation for display data
INTEL CORP196 citations97
US6867779B1Mar 15, 2005
Image rendering
INTEL CORP48 citations96
US6078339AJun 20, 2000
Mutual exclusion of drawing engine execution on a graphics device
INTEL CORP78 citations95
US5761444AJun 2, 1998
Method and apparatus for dynamically deferring transactions
INTEL CORP55 citations95
US6496193B1Dec 17, 2002
Method and apparatus for fast loading of texture data into a tiled memory
INTEL CORP104 citations93
US7321369B2Jan 22, 2008
Method and apparatus for synchronizing processing of multiple asynchronous client queues on a graphics controller device
INTEL CORP31 citations92
US7051172B2May 23, 2006
Memory arbiter with intelligent page gathering logic
INTEL CORP30 citations92
US6792516B2Sep 14, 2004
Memory arbiter with intelligent page gathering logic
INTEL CORP26 citations92
US6650332B2Nov 18, 2003
Method and apparatus for implementing dynamic display memory
INTEL CORP19 citations92
US6560657B1May 6, 2003
System and method for controlling peripheral devices
INTEL CORP34 citations92
US6362826B1Mar 26, 2002
Method and apparatus for implementing dynamic display memory
INTEL CORP33 citations92
US6141023AOct 31, 2000
Efficient display flip
INTEL CORP51 citations92
US6026451AFeb 15, 2000
System for controlling a dispatch of requested data packets by generating size signals for buffer space availability and preventing a dispatch prior to a data request granted signal asserted
INTEL CORP39 citations92
US6633299B1Oct 14, 2003
Method and apparatus for implementing smart allocation policies for a small frame buffer cache serving 3D and 2D streams
INTEL CORP35 citations90
US6330646B1Dec 11, 2001
Arbitration mechanism for a computer system having a unified memory architecture
INTEL CORP36 citations90
US6724389B1Apr 20, 2004
Multiplexing digital video out on an accelerated graphics port interface
INTEL CORP37 citations89
US6538650B1Mar 25, 2003
Efficient TLB entry management for the render operands residing in the tiled memory
INTEL CORP26 citations86
US7173627B2Feb 6, 2007
Apparatus, method and system with a graphics-rendering engine having a graphics context manager
INTEL CORP11 citations84
US7035984B2Apr 25, 2006
Memory arbiter with grace and ceiling periods and intelligent page gathering logic
INTEL CORP12 citations84
US6954208B2Oct 11, 2005
Depth write disable for rendering
INTEL CORP13 citations84
US6199149B1Mar 6, 2001
Overlay counter for accelerated graphics port
INTEL CORP16 citations83
US6449702B1Sep 10, 2002
Memory bandwidth utilization through multiple priority request policy for isochronous data streams
INTEL CORP14 citations81
US6999091B2Feb 14, 2006
Dual memory channel interleaving for graphics and video
INTEL CORP18 citations79
US6995773B2Feb 7, 2006
Automatic memory management
INTEL CORP7 citations74
US6747657B2Jun 8, 2004
Depth write disable for zone rendering
INTEL CORP7 citations74
US6747658B2Jun 8, 2004
Automatic memory management for zone rendering
INTEL CORP9 citations74
US7230627B2Jun 12, 2007
Optimized memory addressing
INTEL CORP6 citations73
US5696768ADec 9, 1997
Method and apparatus for data storage array tracking
INTEL CORP12 citations73
US9542336B2Jan 10, 2017
Isochronous agent data pinning in a multi-level memory system
INTEL CORP3 citations71
US6067090AMay 23, 2000
Data skew management of multiple 3-D graphic operand requests
INTEL CORP11 citations67
US7348986B2Mar 25, 2008
Image rendering
INTEL CORP3 citations63
US7164427B2Jan 16, 2007
Apparatus, method and system with a graphics-rendering engine having a time allocator
INTEL CORP4 citations63
US6629253B1Sep 30, 2003
System for efficient management of memory access requests from a planar video overlay data stream using a time delay
INTEL CORP4 citations62
US6025855AFeb 15, 2000
Store double word and status word write graphics primitives
INTEL CORP5 citations62
US7612780B2Nov 3, 2009
Optimized memory addressing
INTEL CORP1 citations51
US7120774B2Oct 10, 2006
Efficient management of memory access requests from a video data stream
INTEL CORP0 citations51