Inventor
BEAUSANG JAMES
US11 patents
Patents
11 patentsUS6449755B1Sep 10, 2002
Instruction signature and primary input and primary output extraction within an IEEE 1149.1 compliance checker
SYNOPSYS INC88 citations97
US5903466AMay 11, 1999
Constraint driven insertion of scan logic for implementing design for test within an integrated circuit design
SYNOPSYS INC162 citations97
US5828579AOct 27, 1998
Scan segment processing within hierarchical scan architecture for design for test applications
SYNOPSYS INC100 citations97
US5696771ADec 9, 1997
Method and apparatus for performing partial unscan and near full scan within design for test applications
SYNOPSYS INC112 citations97
US6106568AAug 22, 2000
Hierarchical scan architecture for design for test applications
SYNOPSYS INC120 citations96
US5831868ANov 3, 1998
Test ready compiler for design for test synthesis
SYNOPSYS INC60 citations96
US5703789ADec 30, 1997
Test ready compiler for design for test synthesis
SYNOPSYS INC78 citations96
US6067650AMay 23, 2000
Method and apparatus for performing partial unscan and near full scan within design for test applications
SYNOPSYS INC54 citations95
US5949692ASep 7, 1999
Hierarchical scan architecture for design for test applications
SYNOPSYS INC89 citations94
US6141790AOct 31, 2000
Instructions signature and primary input and primary output extraction within an IEEE 1149.1 compliance checker
SYNOPSYS INC30 citations92
US6012155AJan 4, 2000
Method and system for performing automatic extraction and compliance checking of an IEEE 1149.1 standard design within a netlist
SYNOPSYS INC43 citations92