Inventor
CLEEREMAN KEVIN C
US6 patents
Patents
6 patentsUS5980092ANov 9, 1999
Method and apparatus for optimizing a gated clock structure using a standard optimization tool
UNISYS CORP73 citations94
US5956256ASep 21, 1999
Method and apparatus for optimizing a circuit design having multi-paths therein
UNISYS CORP47 citations91
US5940604AAug 17, 1999
Method and apparatus for monitoring the performance of a circuit optimization tool
UNISYS CORP20 citations91
US5864487AJan 26, 1999
Method and apparatus for identifying gated clocks within a circuit design using a standard optimization tool
UNISYS CORP49 citations91
US6026220AFeb 15, 2000
Method and apparatus for incremntally optimizing a circuit design
UNISYS CORP50 citations88
US5960184ASep 28, 1999
Method and apparatus for providing optimization parameters to a logic optimizer tool
UNISYS CORP14 citations72