Inventor
IMORI HIROMITSU
JP7 patents
Patents
7 patentsUS6131145AOct 10, 2000
Information processing unit and method for controlling a hierarchical cache utilizing indicator bits to control content of prefetching operations
HITACHI LTD108 citations98
US7028159B2Apr 11, 2006
Processing device with prefetch instructions having indicator bits specifying cache levels for prefetching
HITACHI LTD49 citations95
US6381679B1Apr 30, 2002
Information processing system with prefetch instructions having indicator bits specifying cache levels for prefetching
HITACHI LTD65 citations95
US6598126B2Jul 22, 2003
Processing device which prefetches instructions having indicator bits specifying cache levels for prefetching
HITACHI LTD6 citations73
US6598127B2Jul 22, 2003
Information processing system with prefetch instructions having indicator bits specifying a quantity of operand data for prefetching
HITACHI LTD6 citations73
US5438669AAug 1, 1995
Data processor with improved loop handling utilizing improved register allocation
HITACHI LTD15 citations70
US7028160B2Apr 11, 2006
Processing device with prefetch instructions having indicator bits specifying cache levels for prefetching
HITACHI LTD0 citations51