Inventor
CHEN JONG
TW29 patents
⚠️ This page may combine multiple inventors who share the name “CHEN JONG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TAIWAN SEMICONDUCTOR MFG
26 patentsUS7459792B2Dec 2, 2008
Via layout with via groups placed in interlocked arrangement
TAIWAN SEMICONDUCTOR MFG140 citations98
US6127227AOct 3, 2000
Thin ONO thickness control and gradual gate oxidation suppression by b. N.su2 treatment in flash memory
TAIWAN SEMICONDUCTOR MFG97 citations98
US6074915AJun 13, 2000
Method of making embedded flash memory with salicide and sac structure
TAIWAN SEMICONDUCTOR MFG146 citations98
US6013551AJan 11, 2000
Method of manufacture of self-aligned floating gate, flash memory cell and device manufactured thereby
TAIWAN SEMICONDUCTOR MFG98 citations98
US6153494ANov 28, 2000
Method to increase the coupling ratio of word line to floating gate by lateral coupling in stacked-gate flash
TAIWAN SEMICONDUCTOR MFG70 citations96
US6124177ASep 26, 2000
Method for making deep sub-micron mosfet structures having improved electrical characteristics
TAIWAN SEMICONDUCTOR MFG74 citations96
US6037223AMar 14, 2000
Stack gate flash memory cell featuring symmetric self aligned contact structures
TAIWAN SEMICONDUCTOR MFG68 citations96
US6724036B1Apr 20, 2004
Stacked-gate flash memory cell with folding gate and increased coupling ratio
TAIWAN SEMICONDUCTOR MFG40 citations93
US6437397B1Aug 20, 2002
Flash memory cell with vertically oriented channel
TAIWAN SEMICONDUCTOR MFG26 citations93
US6348382B1Feb 19, 2002
Integration process to increase high voltage breakdown performance
TAIWAN SEMICONDUCTOR MFG29 citations93
US6297098B1Oct 2, 2001
Tilt-angle ion implant to improve junction breakdown in flash memory application
TAIWAN SEMICONDUCTOR MFG38 citations93
US6251744B1Jun 26, 2001
Implant method to improve characteristics of high voltage isolation and high voltage breakdown
TAIWAN SEMICONDUCTOR MFG32 citations93
US6172395B1Jan 9, 2001
Method of manufacture of self-aligned floating gate, flash memory cell and device manufactured thereby
TAIWAN SEMICONDUCTOR MFG37 citations93
US6130168AOct 10, 2000
Using ONO as hard mask to reduce STI oxide loss on low voltage device in flash or EPROM process
TAIWAN SEMICONDUCTOR MFG47 citations93
US6127226AOct 3, 2000
Method for forming vertical channel flash memory cell using P/N junction isolation
TAIWAN SEMICONDUCTOR MFG34 citations93
US6078076AJun 20, 2000
Vertical channels in split-gate flash memory cell
TAIWAN SEMICONDUCTOR MFG30 citations93
US6011288AJan 4, 2000
Flash memory cell with vertical channels, and source/drain bus lines
TAIWAN SEMICONDUCTOR MFG33 citations93
US6001687ADec 14, 1999
Process for forming self-aligned source in flash cell using SiN spacer as hard mask
TAIWAN SEMICONDUCTOR MFG31 citations93
US5970341AOct 19, 1999
Method for forming vertical channels in split-gate flash memory cell
TAIWAN SEMICONDUCTOR MFG20 citations93
US5960284ASep 28, 1999
Method for forming vertical channel flash memory cell and device manufactured thereby
TAIWAN SEMICONDUCTOR MFG19 citations93
US6261905B1Jul 17, 2001
Flash memory structure with stacking gate formed using damascene-like structure
TAIWAN SEMICONDUCTOR MFG26 citations89
US6066874AMay 23, 2000
Flash memory cell with vertical channels, and source/drain bus lines
TAIWAN SEMICONDUCTOR MFG10 citations74
US6190969B1Feb 20, 2001
Method to fabricate a flash memory cell with a planar stacked gate
TAIWAN SEMICONDUCTOR MFG3 citations63
US6063664AMay 16, 2000
Method of making EEPROM with trenched structure
TAIWAN SEMICONDUCTOR MFG2 citations63
US6340638B1Jan 22, 2002
Method for forming a passivation layer on copper conductive elements
TAIWAN SEMICONDUCTOR MFG6 citations61
US6495880B2Dec 17, 2002
Method to fabricate a flash memory cell with a planar stacked gate
TAIWAN SEMICONDUCTOR MFG0 citations52