P

Inventor

SETO PAK-LUNG

US46 patents
⚠️ This page may combine multiple inventors who share the name “SETO PAK-LUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

37 patents
US7376147B2May 20, 2008

Adaptor supporting different protocols

INTEL CORP67 citations97
US7155546B2Dec 26, 2006

Multiple physical interfaces in a slot of a storage enclosure to support different storage interconnect architectures

INTEL CORP55 citations96
US7738502B2Jun 15, 2010

Signal noise filtering in a serial interface

INTEL CORP35 citations92
US7502865B2Mar 10, 2009

Addresses assignment for adaptor interfaces

INTEL CORP23 citations92
US7376789B2May 20, 2008

Wide-port context cache apparatus, systems, and methods

INTEL CORP48 citations92
US7373443B2May 13, 2008

Multiple interfaces in a storage enclosure

INTEL CORP30 citations92
US7363395B2Apr 22, 2008

Intermediate device capable of communicating using different communication protocols

INTEL CORP26 citations92
US7093033B2Aug 15, 2006

Integrated circuit capable of communicating using different communication protocols

INTEL CORP46 citations90
US7415549B2Aug 19, 2008

DMA completion processing mechanism

INTEL CORP44 citations89
US7953917B2May 31, 2011

Communications protocol expander

INTEL CORP8 citations84
US7809068B2Oct 5, 2010

Integrated circuit capable of independently operating a plurality of communication channels

INTEL CORP10 citations84
US7453904B2Nov 18, 2008

Cut-through communication protocol translation bridge

INTEL CORP12 citations84
US7373442B2May 13, 2008

Method for using an expander to connect to different storage interconnect architectures

INTEL CORP10 citations84
US7353302B2Apr 1, 2008

Selectable communication control between devices communicating using a serial attached SCSI (SAS) protocol

INTEL CORP17 citations84
US7797463B2Sep 14, 2010

Hardware assisted receive channel frame handling via data offset comparison in SAS SSP wide port applications

INTEL CORP9 citations83
US7747788B2Jun 29, 2010

Hardware oriented target-side native command queuing tag management

INTEL CORP10 citations83
US7643410B2Jan 5, 2010

Method and apparatus for managing a connection in a connection orientated environment

INTEL CORP9 citations83
US7450588B2Nov 11, 2008

Storage network out of order packet reordering mechanism

INTEL CORP13 citations83
US7451255B2Nov 11, 2008

Hardware port scheduler (PTS) having register to indicate which of plurality of protocol engines PTS is to support

INTEL CORP14 citations82
US7221531B2May 22, 2007

Staggered spin-up disable mechanism

INTEL CORP12 citations82
US7178054B2Feb 13, 2007

Frame validation

INTEL CORP10 citations81
US7774575B2Aug 10, 2010

Integrated circuit capable of mapping logical block address data across multiple domains

INTEL CORP14 citations80
US7650540B2Jan 19, 2010

Detecting and differentiating SATA loopback modes

INTEL CORP7 citations73
US7366802B2Apr 29, 2008

Method in a frame based system for reserving a plurality of buffers based on a selected communication protocol

INTEL CORP5 citations63
US7272745B2Sep 18, 2007

Data protection system

INTEL CORP5 citations63
US8032675B2Oct 4, 2011

Dynamic memory buffer allocation method and system

INTEL CORP2 citations62
US7805543B2Sep 28, 2010

Hardware oriented host-side native command queuing tag management

INTEL CORP4 citations62
US7730239B2Jun 1, 2010

Data buffer management in a resource limited environment

INTEL CORP3 citations62
US7412540B2Aug 12, 2008

Data encoding and decoding in a data storage system

INTEL CORP6 citations62
US7366817B2Apr 29, 2008

Frame order processing apparatus, systems, and methods

INTEL CORP2 citations62
US7984208B2Jul 19, 2011

Method using port task scheduler

INTEL CORP2 citations60
US7447826B2Nov 4, 2008

Receive buffer in a data storage system

INTEL CORP4 citations60
US7676604B2Mar 9, 2010

Task context direct indexing in a protocol engine

INTEL CORP3 citations57
US8370581B2Feb 5, 2013

System and method for dynamic data prefetching

INTEL CORP0 citations52
US7231581B2Jun 12, 2007

Communicating using a partial block in a frame

INTEL CORP0 citations52
US7620751B2Nov 17, 2009

Command scheduling and affiliation management for serial attached storage devices

INTEL CORP1 citations51
US7516257B2Apr 7, 2009

Mechanism to handle uncorrectable write data errors

INTEL CORP0 citations41

MAXTOR CORP

1 patent

FOONG ANNIE

1 patent

DUERK VICKY

1 patent

CHANG NAI-CHIH

1 patent

LAU VICTOR

1 patent

CHANG NAICHIH

1 patent

INTER CORP

1 patent

DUERK VICKY P

1 patent

SETO PAK-LUNG

1 patent