Inventor

LEE CHULKYU

US61 patents

⚠️ This page may combine multiple inventors who share the name “LEE CHULKYU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEE CHULKYU

QUALCOMM INC

N-phase polarity output pin mode multiplexer

C-PHY receiver equalization

Programmable pre-emphasis circuit for MIPI C-PHY

Time based equalization for a C-PHY 3-phase transmitter

Multiphase clock data recovery for a 3-phase interface

Multi-wire signaling with matched propagation delay among wire pairs

Multiphase clock data recovery circuit calibration

N-phase polarity output pin mode multiplexer

N-phase phase and polarity encoded serial interface

Multiphase clock data recovery with adaptive tracking for a multi-wire, multi-phase interface

Calibration pattern and duty-cycle distortion correction for clock data recovery in a multi-wire, multi-phase interface

Run-length detection and correction

Circuit to recover a clock signal from multiple wire data signals that changes state every state cycle and is immune to data inter-lane skew as well as data state transition glitches

Transcoding method for multi-wire signaling that embeds clock information in transition of signal state

Compact and fast N-factorial single data rate clock and data recovery circuits

Efficient N-factorial differential signaling termination network

Level shifter having low duty cycle distortion

Clock and data recovery for multi-phase, multi-level encoding

Intelligent equalization for a three-transmitter multi-phase system

N-phase phase and polarity encoded serial interface

Analog-mixed signal circuit cells with universal Fin pitch and poly pitch

C-PHY half-rate wire state encoder and decoder

Independent pair 3-phase eye sampling circuit

Serializer and deserializer for odd ratio parallel data bus

Feed-forward bias circuit

Three phase clock recovery delay calibration

Driver architecture for multiphase and amplitude encoding transmitters

Reducing transmitter encoding jitter in a C-PHY interface using multiple clock phases to launch symbols

Low power physical layer driver topologies

Multi-wire signaling with matched propagation delay among wire pairs

Charge pump based low dropout regulator

N-phase signal transition alignment

N-phase signal transition alignment

Specifying a 3-phase or N-phase eye pattern

Multi-phase clock generation method

Sharing hardware resources between D-PHY and N-factorial termination networks

C-PHY half-rate wire state encoder and decoder

N-phase phase and polarity encoded serial interface

Termination for high-frequency transmission lines

Unit interval jitter improvement in a C-PHY interface

N-phase signal transition alignment

Transcoding method for multi-wire signaling that embeds clock information in transition of signal state

Voltage mode driver circuit for N-phase systems

MICRON TECHNOLOGY INC

Distributed feedback in scale up signal paths

Apparatus with speed selection mechanism and method for operating

Self-calibration in a memory device

NAT INSTITUTE OF METEOROLOGICAL SCIENCES

Method and system of analyzing ingredients of artificial rainfall for verification of cloud seeding effect

Method and apparatus for calibrating CTD observation information

Drop assist apparatus of unmanned marine observation apparatus and controlling method thereof

LEE CHULKYU

Low power deserializer and demultiplexing method