Inventor
HSU YING-YU
TW24 patents
⚠️ This page may combine multiple inventors who share the name “HSU YING-YU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TAIWAN SEMICONDUCTOR MFG CO LTD
14 patentsUS9965409B2May 8, 2018
Data sampling alignment method for memory interface
TAIWAN SEMICONDUCTOR MFG CO LTD5 citations83
US9419615B2Aug 16, 2016
Driver circuit
TAIWAN SEMICONDUCTOR MFG CO LTD10 citations82
US10162926B2Dec 25, 2018
Stacked chip layout having overlapped regions
TAIWAN SEMICONDUCTOR MFG CO LTD2 citations72
US9766288B2Sep 19, 2017
On-chip eye diagram capture
TAIWAN SEMICONDUCTOR MFG CO LTD4 citations72
US9503061B2Nov 22, 2016
System and method for calibrating chips in a 3D chip stack architecture
TAIWAN SEMICONDUCTOR MFG CO LTD1 citations63
US9231585B2Jan 5, 2016
System and method for calibrating chips in a 3D chip stack architecture
TAIWAN SEMICONDUCTOR MFG CO LTD1 citations63
US11188701B2Nov 30, 2021
Stacked chip layout
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US9267988B2Feb 23, 2016
On-chip eye diagram capture
TAIWAN SEMICONDUCTOR MFG CO LTD2 citations62
US9748241B2Aug 29, 2017
Semiconductor device for simultaneous operation at two temperature ranges
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations52
US9099990B2Aug 4, 2015
High speed communication interface with an adaptive swing driver to reduce power consumption
TAIWAN SEMICONDUCTOR MFG CO LTD1 citations52
US10540473B2Jan 21, 2020
Stacked chip layout and method of making the same
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations51
US9619409B2Apr 11, 2017
Data sampling alignment method for memory inferface
TAIWAN SEMICONDUCTOR MFG CO LTD1 citations51
US9495500B2Nov 15, 2016
Method of making stacked chip layout
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations51
US9564900B2Feb 7, 2017
Supply boost device
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations50
HSU YING-YU
4 patentsUS8410818B1Apr 2, 2013
High speed communication interface with an adaptive swing driver to reduce power consumption
HSU YING-YU16 citations91
US8866508B2Oct 21, 2014
System and method for calibrating chips in a 3D chip stack architecture
HSU YING-YU0 citations51
US8324972B2Dec 4, 2012
Front-end circuit of low supply-voltage memory interface receiver
HSU YING-YU0 citations50
US9363115B2Jun 7, 2016
System and method for aligning data bits
HSU YING-YU0 citations38
TAIWAN SEMICONDUCTOR MFG
3 patentsUS9159716B2Oct 13, 2015
Stacked chip layout having overlapped active circuit blocks
TAIWAN SEMICONDUCTOR MFG6 citations83
US8362870B2Jan 29, 2013
Impedance calibration circuit with uniform step heights
TAIWAN SEMICONDUCTOR MFG4 citations62
US7940079B2May 10, 2011
Integrated circuits and methods for providing impedance of driver to drive data
TAIWAN SEMICONDUCTOR MFG4 citations62
MEDIATEK INC
3 patentsUS10158352B2Dec 18, 2018
Delay signal generating apparatus using glitch free digitally controlled delay line and associated delay signal generating method
MEDIATEK INC3 citations70
US10447466B2Oct 15, 2019
Transceiver and clock generation module
MEDIATEK INC2 citations69
US11569805B2Jan 31, 2023
Minimum intrinsic timing utilization auto alignment on multi-die system
MEDIATEK INC0 citations51