Inventor

HUA XUEFENG

US17 patents

⚠️ This page may combine multiple inventors who share the name “HUA XUEFENG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HUA XUEFENG

IBM

Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (S0I) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor

Source/drain junction for high performance MOSFET formed by selective EPI process

Lithography for pitch reduction

Reduced floating body effect without impact on performance-enhancing stress

LAM RES CORP

Plasma-exclusion-zone rings for processing notched wafers

Arcing reduction in wafer bevel edge plasma processing

Wafer edge deposition for wafer level packaging

In-situ wafer thickness and gap monitoring using through beam laser sensor

CHENG KANGGUO

Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (SOI) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor

Device having and method for forming fins with multiple widths for an integrated circuit

Device having and method for forming fins with multiple widths

ARNOLD JOHN C

Transistor devices and methods of making

Transistor devices and methods of making

FALTERMEIER JOHNATHAN E

Stress enhanced transistor devices and methods of making

Stress enhanced transistor devices and methods of making

UNIV MARYLAND

Method and system for nanoscale plasma processing of objects

APPLIED MATERIALS INC

Methods of surface interface engineering