Inventor

DHONG SANG H

US55 patents

Patents

50 patents

US5021355AJun 4, 1991

Folder Bitline DRAM having access transistors stacked above trench storage capacitors, each such transistor employing a planar semiconductor body which spans adjacent capacitors

IBM45 citations96

US5292678AMar 8, 1994

Forming a bit line configuration for semiconductor memory

IBM68 citations96

US5289432AFeb 22, 1994

Dual-port static random access memory cell

IBM63 citations96

US5250829AOct 5, 1993

Double well substrate plate trench DRAM cell array

IBM47 citations96

US5214603AMay 25, 1993

Folded bitline, ultra-high density dynamic random access memory having access transistors stacked above trench storage capacitors

IBM104 citations96

US5212616AMay 18, 1993

Voltage regulation and latch-up protection circuits

IBM81 citations96

US5204280AApr 20, 1993

Process for fabricating multiple pillars inside a dram trench for increased capacitor surface

IBM88 citations96

US5170243ADec 8, 1992

Bit line configuration for semiconductor memory

IBM54 citations96

US5144165ASep 1, 1992

CMOS off-chip driver circuits

IBM74 citations96

US4922128AMay 1, 1990

Boost clock circuit for driving redundant wordlines and sample wordlines

IBM82 citations96

US5107459AApr 21, 1992

Stacked bit-line architecture for high density cross-point memory cell array

IBM165 citations95

US4954854ASep 4, 1990

Cross-point lightly-doped drain-source trench transistor and fabrication process therefor

IBM131 citations95

US4920065AApr 24, 1990

Method of making ultra dense dram cells

IBM144 citations95

US5253202AOct 12, 1993

Word line driver circuit for dynamic random access memories

IBM48 citations93

US5185719AFeb 9, 1993

High speed dynamic, random access memory with extended reset/precharge time

IBM27 citations93

US5075571ADec 24, 1991

PMOS wordline boost cricuit for DRAM

IBM23 citations93

US4988637AJan 29, 1991

Method for fabricating a mesa transistor-trench capacitor memory cell structure

IBM53 citations93

US4816706AMar 28, 1989

Sense amplifier with improved bitline precharging for dynamic random access memory

IBM71 citations93

US5453953ASep 26, 1995

Bandgap voltage reference generator

IBM35 citations92

US5339274AAug 16, 1994

Variable bitline precharge voltage sensing technique for DRAM structures

IBM37 citations92

US5280452AJan 18, 1994

Power saving semsing circuits for dynamic random access memory

IBM25 citations92

US5268871ADec 7, 1993

Power supply tracking regulator for a memory array

IBM36 citations92

US5257232AOct 26, 1993

Sensing circuit for semiconductor memory with limited bitline voltage swing

IBM30 citations92

US5162668ANov 10, 1992

Small dropout on-chip voltage regulators with boosted power supply

IBM54 citations92

US5157634AOct 20, 1992

Dram having extended refresh time

IBM48 citations92

US4999518AMar 12, 1991

MOS switching circuit having gate enhanced lateral bipolar transistor

IBM32 citations92

US4954731ASep 4, 1990

Wordline voltage boosting circuits for complementary MOSFET dynamic memories

IBM27 citations92

US4927779AMay 22, 1990

Complementary metal-oxide-semiconductor transistor and one-capacitor dynamic-random-access memory cell and fabrication process therefor

IBM38 citations92

US4910709AMar 20, 1990

Complementary metal-oxide-semiconductor transistor and one-capacitor dynamic-random-access memory cell

IBM51 citations92

US7447602B1Nov 4, 2008

System and method for sorting processors based on thermal design point

IBM27 citations91

US7486096B2Feb 3, 2009

Method and apparatus for testing to determine minimum operating voltages in electronic devices

IBM9 citations84

US5881274AMar 9, 1999

Method and apparatus for performing add and rotate as a single instruction within a processor

IBM17 citations84

US8381006B2Feb 19, 2013

Reducing power requirements of a multiple core processor

IBM16 citations83

US5331189AJul 19, 1994

Asymmetric multilayered dielectric material and a flash EEPROM using the same

IBM18 citations80

US6910165B2Jun 21, 2005

Digital random noise generator

IBM7 citations74

US5541887AJul 30, 1996

Multiple port cells with improved testability

IBM6 citations74

US5483179AJan 9, 1996

Data output drivers with pull-up devices

IBM7 citations74

US5418477AMay 23, 1995

Data output buffer pull-down circuit for TTL interface

IBM11 citations74

US5343092AAug 30, 1994

Self-biased feedback-controlled active pull-down signal switching

IBM15 citations74

US5034787AJul 23, 1991

Structure and fabrication method for a double trench memory cell device

IBM16 citations74

US7739573B2Jun 15, 2010

Voltage identifier sorting

IBM7 citations73

US7610531B2Oct 27, 2009

Modifying a test pattern to control power supply noise

IBM7 citations73

US5635858AJun 3, 1997

Zero-stopping incrementers

IBM7 citations73

US5451535ASep 19, 1995

Method for manufacturing a memory cell

IBM8 citations71

US4894697AJan 16, 1990

Ultra dense dram cell and its method of fabrication

IBM19 citations71

US7423921B2Sep 9, 2008

Method and apparatus for wordline redundancy control of memory in an information handling system

IBM3 citations63

US5321647AJun 14, 1994

Semiconductor memory device and operational method with reduced well noise

IBM6 citations63

Showing the top 50 of 55 patents by PatentIndex Score.

DHONG SANG H

Patents

Method of fabricating cross-point lightly-doped drain-source trench transistor

Method of forming double well substrate plate trench DRAM cell array

Power supply tracking regulator for a memory array

Folder Bitline DRAM having access transistors stacked above trench storage capacitors, each such transistor employing a planar semiconductor body which spans adjacent capacitors

Forming a bit line configuration for semiconductor memory

Dual-port static random access memory cell

Double well substrate plate trench DRAM cell array

Folded bitline, ultra-high density dynamic random access memory having access transistors stacked above trench storage capacitors

Voltage regulation and latch-up protection circuits

Process for fabricating multiple pillars inside a dram trench for increased capacitor surface

Bit line configuration for semiconductor memory

CMOS off-chip driver circuits

Boost clock circuit for driving redundant wordlines and sample wordlines

Stacked bit-line architecture for high density cross-point memory cell array

Cross-point lightly-doped drain-source trench transistor and fabrication process therefor

Method of making ultra dense dram cells

Word line driver circuit for dynamic random access memories

High speed dynamic, random access memory with extended reset/precharge time

PMOS wordline boost cricuit for DRAM

Method for fabricating a mesa transistor-trench capacitor memory cell structure

Sense amplifier with improved bitline precharging for dynamic random access memory

Bandgap voltage reference generator

Variable bitline precharge voltage sensing technique for DRAM structures

Power saving semsing circuits for dynamic random access memory

Power supply tracking regulator for a memory array

Sensing circuit for semiconductor memory with limited bitline voltage swing

Small dropout on-chip voltage regulators with boosted power supply

Dram having extended refresh time

MOS switching circuit having gate enhanced lateral bipolar transistor

Wordline voltage boosting circuits for complementary MOSFET dynamic memories

Complementary metal-oxide-semiconductor transistor and one-capacitor dynamic-random-access memory cell and fabrication process therefor

Complementary metal-oxide-semiconductor transistor and one-capacitor dynamic-random-access memory cell

System and method for sorting processors based on thermal design point

Method and apparatus for testing to determine minimum operating voltages in electronic devices

Method and apparatus for performing add and rotate as a single instruction within a processor

Reducing power requirements of a multiple core processor

Asymmetric multilayered dielectric material and a flash EEPROM using the same

Digital random noise generator

Multiple port cells with improved testability

Data output drivers with pull-up devices

Data output buffer pull-down circuit for TTL interface

Self-biased feedback-controlled active pull-down signal switching

Structure and fabrication method for a double trench memory cell device

Voltage identifier sorting

Modifying a test pattern to control power supply noise

Zero-stopping incrementers

Method for manufacturing a memory cell

Ultra dense dram cell and its method of fabrication

Method and apparatus for wordline redundancy control of memory in an information handling system

Semiconductor memory device and operational method with reduced well noise