Inventor

ARIMA HIDEAKI

JP59 patents

⚠️ This page may combine multiple inventors who share the name “ARIMA HIDEAKI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ARIMA HIDEAKI

MITSUBISHI ELECTRIC CORP

Multi-layered interconnection structure for a semiconductor device

Semiconductor device including retrograde well structure with suppressed substrate bias effects

Semiconductor device comprising capacitor and method of fabricating the same

Semiconductor device having capacitor and manufacturing method therefor

DRAM having peripheral circuitry in which source-drain interconnection contact of a MOS transistor is made small by utilizing a pad layer and manufacturing method thereof

Electrically programmable non-volatile semiconductor memory device and manufacturing method thereof

Multi-layered interconnection structure for a semiconductor device and manufactured method thereof

Content addressable memory device

Method of manufacturing semiconductor memory device

Method of producing semiconductor device

Electrically programmable non-volatile memory device and manufacturing method thereof

Integrated circuit having a memory cell transistor with a gate oxide layer which is thicker than the gate oxide layer of a peripheral circuit transistor

Method of manufacturing stacked capacitors in a DRAM with reduced isolation region between adjacent capacitors

Method of manufacturing a DRAM having peripheral circuitry in which source drain interconnection contact of a MOS transistor is made small by utilizing a pad layer

Method of manufacturing a stacked capacitor in a dram

Method of manufacturing semiconductor device having a capacitor

Semiconductor device having retrograde well and diffusion-type well

Semiconductor memory device having a plurality of well regions of different conductivities

Dynamic random access memory having stacked type capacitor and manufacturing method therefor

Method of manufacturing a semiconductor memory device with multiple device forming regions

Semiconductor memory device having a peripheral wall at the boundary region of a memory cell array region and a peripheral circuit region

Electrically programmable non-volatie semiconductor memory device

MIS-type semiconductor device of LDD structure and manufacturing method thereof

Method of manufacturing non-volatile semiconductor memory device

Semiconductor memory device

Field effect transistor having impurity regions of different depths and manufacturing method thereof

Field effect transistor having impurity regions of different depths and manufacturing method thereof

Method of manufacturing field effect transistor having a multilayer interconnection layer therein with tapered sidewall insulation

Semiconductor memory device

Manufacturing method of an electrically programmable non-volatile memory device having the floating gate extending over the control gate

Dynamic random access memory having stacked type capacitor and manufacturing method therefor

Field effect transistor having impurity regions of different depths and manufacturing method thereof

Non-volatile semiconductor memory device using contact hole connection

Semiconductor device with thermally oxidized insulating and arsenic diffusion layers

DRAM having peripheral circuitry in which source-drain interconnection contact of a MOS transistor is made small by utilizing a pad layer and manufacturing method thereof

Semiconductor memory device and method of manufacturing the same

Method of manufacturing a semiconductor device having a capacitor

DRAM having peripheral circuitry in which source-drain interconnection contact of a MOS transistor is made small by utilizing a pad layer and manufacturing method thereof

Semiconductor memory device having cylindrical capacitor and manufacturing method thereof

Method of making a semiconductor integrated device having gate sidewall structure

Semiconductor device having a polysilicon capacitor with large grain diameter

Semiconductor device having gate electrode spacing dependent upon gate side wall insulating dimension

Non-volatile semiconductor memory device and method of manufacturing the same

Method of device isolation using polysilicon pad LOCOS method

RENESAS TECH CORP

Semiconductor device comprising capacitor and method of fabricating the same

Semiconductor device comprising a highly-reliable, constant capacitance capacitor

Semiconductor device comprising capacitor and method of fabricating the same

Semiconductor device comprising a highly-reliable, constant capacitance capacitor

Semiconductor device comprising capacitor and method of fabricating the same

RENESAS ELECTRONICS CORP

Semiconductor device comprising capacitor and method of fabricating the same