Inventor

KOMODA MICHIO

JP22 patents

⚠️ This page may combine multiple inventors who share the name “KOMODA MICHIO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KOMODA MICHIO

MITSUBISHI ELECTRIC CORP

Apparatus for computing power consumption of MOS transistor logic function block

Gate delay calculation apparatus and method thereof using parameter expressing RC model source resistance value

Multiplier circuit and division circuit with a round-off function

Semiconductor integrated circuit and test pattern generation method therefor

Pipeline circuit with a test circuit with small circuit scale and an automatic test pattern generating method for testing the same

Logic synthesizer

Logic simulator

Logic simulator

Apparatus for calculating delay time in logic functional blocks

Master slice LSI with integrated fault detection circuitry

Wiring data generation method and wiring data generation apparatus allowing inconsistency between block internal line and block external lines

Semiconductor integrated circuit device

Test circuit and method for DC testing LSI capable of preventing simultaneous change of signals

Multiplier circuit with rounding-off function

Method of producing load for delay time calculation and recording medium

RENESAS TECH CORP

Circuit modification method

Clock forming method for semiconductor integrated circuit and program product for the method

Delay time estimation method and recording medium storing estimation program

Method of formulating load model for glitch analysis and recording medium with the method recorded thereon

Delay calculation method capable of calculating delay time with small margin of error

SYNOPSYS INC

Method for minimizing ground bounce during DC parametric tests using boundary scan register

MITSUBISHI DENKI KAISHA KITAIT

CMOS semiconductor logic circuit with multiple input gates