Inventor
RUBINSTEIN ASAF
IL16 patents
⚠️ This page may combine multiple inventors who share the name “RUBINSTEIN ASAF”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
15 patentsUS9559726B2Jan 31, 2017
Use of error correcting code to carry additional data bits
INTEL CORP7 citations81
US10055360B2Aug 21, 2018
Apparatus and method for shared least recently used (LRU) policy between multiple cache levels
INTEL CORP3 citations71
US9710054B2Jul 18, 2017
Programmable power management agent
INTEL CORP2 citations71
US10296333B2May 21, 2019
SIMD variable shift and rotate using control manipulation
INTEL CORP5 citations68
US11042315B2Jun 22, 2021
Dynamically programmable memory test traffic router
INTEL CORP0 citations62
US10915453B2Feb 9, 2021
Multi level system memory having different caching structures and memory controller that supports concurrent look-up into the different caching structures
INTEL CORP0 citations61
US12591515B2Mar 31, 2026
Reducing memory power usage in far memory
INTEL CORP0 citations58
US10761594B2Sep 1, 2020
Programmable power management agent
INTEL CORP0 citations51
US10657070B2May 19, 2020
Apparatus and method for shared least recently used (LRU) policy between multiple cache levels
INTEL CORP0 citations51
US10324718B2Jun 18, 2019
Packed rotate processors, methods, systems, and instructions
INTEL CORP0 citations51
US10635593B2Apr 28, 2020
Create page locality in cache controller cache allocation
INTEL CORP0 citations49
US10153784B2Dec 11, 2018
Use of error correcting code to carry additional data bits
INTEL CORP0 citations49
US9846648B2Dec 19, 2017
Create page locality in cache controller cache allocation
INTEL CORP0 citations49
US10304418B2May 28, 2019
Operating system transparent system memory abandonment
INTEL CORP0 citations40
US10678706B2Jun 9, 2020
Cache memory with scrubber logic
INTEL CORP0 citations31