Inventor
MU XIAO-CHUN
US29 patents
⚠️ This page may combine multiple inventors who share the name “MU XIAO-CHUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
27 patentsUS6964889B2Nov 15, 2005
Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
INTEL CORP153 citations99
US6902950B2Jun 7, 2005
Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
INTEL CORP251 citations99
US6461895B1Oct 8, 2002
Process for making active interposer for high performance packaging applications
INTEL CORP353 citations99
US6423570B1Jul 23, 2002
Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
INTEL CORP352 citations99
US6271469B1Aug 7, 2001
Direct build-up layer on an encapsulated die package
INTEL CORP711 citations99
US5350484ASep 27, 1994
Method for the anisotropic etching of metal films in the fabrication of interconnects
INTEL CORP275 citations99
US6586822B1Jul 1, 2003
Integrated core microelectronic package
INTEL CORP179 citations98
US6154366ANov 28, 2000
Structures and processes for fabricating moisture resistant chip-on-flex packages
INTEL CORP496 citations98
US5612254AMar 18, 1997
Methods of forming an interconnect on a semiconductor substrate
INTEL CORP478 citations98
US6600364B1Jul 29, 2003
Active interposer technology for high performance CMOS packaging application
INTEL CORP74 citations96
US6586836B1Jul 1, 2003
Process for forming microelectronic packages and intermediate structures formed therewith
INTEL CORP111 citations96
US6365962B1Apr 2, 2002
Flip-chip on flex for high performance packaging applications
INTEL CORP47 citations96
US4980018ADec 25, 1990
Plasma etching process for refractory metal vias
INTEL CORP240 citations96
US5792522AAug 11, 1998
High density plasma physical vapor deposition
INTEL CORP65 citations94
US6798003B2Sep 28, 2004
Reliable adhesion layer interface structure for polymer memory electrode and method of making same
INTEL CORP20 citations93
US6624457B2Sep 23, 2003
Stepped structure for a multi-rank, stacked polymer memory device and method of making same
INTEL CORP18 citations93
US6312830B1Nov 6, 2001
Method and an apparatus for forming an under bump metallization structure
INTEL CORP17 citations92
US6756620B2Jun 29, 2004
Low-voltage and interface damage-free polymer memory device
INTEL CORP21 citations91
US5035768AJul 30, 1991
Novel etch back process for tungsten contact/via filling
INTEL CORP44 citations90
US6960479B2Nov 1, 2005
Stacked ferroelectric memory device and method of making same
INTEL CORP15 citations84
US6858862B2Feb 22, 2005
Discrete polymer memory array and method of making same
INTEL CORP13 citations84
US6524887B2Feb 25, 2003
Embedded recess in polymer memory package and method of making same
INTEL CORP15 citations84
US5167760ADec 1, 1992
Etchback process for tungsten contact/via filling
INTEL CORP13 citations71
US7078240B2Jul 18, 2006
Reliable adhesion layer interface structure for polymer memory electrode and method of making same
INTEL CORP4 citations63
US7018853B1Mar 28, 2006
Stepped structure for a multi-rank, stacked polymer memory device and method of making same
INTEL CORP2 citations63
US6461954B1Oct 8, 2002
Method and an apparatus for forming an under bump metallization structure
INTEL CORP4 citations63
US6952017B2Oct 4, 2005
Low-voltage and interface damage-free polymer memory device
INTEL CORP2 citations61